KSZ8081RNACA
10BASE-T/100BASE-TX PHY with RMII Support
The KSZ8081RNACA is an electronic component from Microchip Technology. 10BASE-T/100BASE-TX PHY with RMII Support. View the full KSZ8081RNACA datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
Key Specifications
| Parameter | Value |
|---|---|
| Duplex | Full |
| Mounting Type | Surface Mount |
| Number of Drivers/Receivers | 1/1 |
| Operating Temperature | 0°C ~ 70°C |
| Package / Case | 24-VFQFN Exposed Pad |
| Protocol | RMII |
| Supplier Device Package | 24-QFN (4x4) |
| Type | Transceiver |
| Supply Voltage | 1.8V, 2.5V, 3.3V |
Overview
Part: Microchip KSZ8081RNA/RND
Type: Ethernet Physical-Layer Transceiver
Key Specs:
- Ethernet Speeds: 10/100 Mbps
- RMII Reference Clock: 50 MHz
- Supply Voltage: 3.3V
- HBM ESD Rating: 6 kV
- Core Regulator: 1.2V
- I/O Voltage Options: 1.8V, 2.5V, 3.3V
Features:
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant
- RMII v1.2 Interface Support
- MDC/MDIO Management Interface
- Auto-Negotiation (10/100 Mbps, Half/Full Duplex)
- HP Auto MDI/MDI-X
- LinkMD® TDR-Based Cable Diagnostics
- Power-Down and Power-Saving Modes
- On-Chip Termination Resistors for Differential Pairs
- Parametric NAND Tree Support for Fault Detection
Applications:
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Package:
- 24-pin QFN: 4 mm x 4 mm
Features
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- RMII v1.2 Interface Support with a 50 MHz Reference Clock Output to MAC, and an Option to Input a 50 MHz Reference Clock
- RMII Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- HBM ESD Rating (6 kV)
- Loopback Modes for Diagnostics
- Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V
- Built-In 1.2V Regulator for Core
- Available in 24-pin 4 mm x 4 mm QFN Package
Applications
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Pin Configuration
FIGURE 2-1: 24-QFN PIN ASSIGNMENT (TOP VIEW)
TABLE 2-1: SIGNALS - KSZ8081RNA/RND
| Pin Number | Pin Name | Type Note 2-1 | Description |
|---|---|---|---|
| 1 | VDD_1.2 | P | 1.2V Core VDD (power supplied by KSZ8081RNA/KSZ8081RND). Decouple with 2.2 μF and 0.1 μF capacitors to ground. |
| 2 | VDDA_3.3 | P | 3.3V Analog VDD. |
| 3 | RXM | I/O | Physical Receive or Transmit Signal (– differential). |
| 4 | RXP | I/O | Physical Receive or Transmit Signal (+ differential). |
| 5 | TXM | I/O | Physical Transmit or Receive Signal (– differential). |
| 6 | TXP | I/O | Physical Transmit or Receive Signal (+ differential). |
| 7 | XO | O | Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator or external clock source is used. |
| 8 | XI | I | RMII – 25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock Input RMII – 50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input For unmanaged mode (power-up default setting): – KSZ8081RNA takes in the 25 MHz crystal/clock on this pin. – KSZ8081RND takes in the 50 MHz clock on this pin. After power-up, both the KSZ8081RNA and KSZ8081RND can be pro grammed to either the 25 MHz mode or 50 MHz mode using PHY Register 1Fh Bit [7]. See also REF_CLK (Pin 16). |
| 9 | REXT | I | Set PHY Transmit Output Current. Connect a 6.49 kΩ resistor to ground on this pin. |
| 10 | MDIO | Ipu/ Opu | Management Interface (MII) Data I/O. This pin has a weak pull-up, is open drain, and requires an external 1.0 kΩ pull-up resistor. |
| 11 | MDC | Ipu | Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO data pin. |
| 12 | RXD1 | Ipd/O | RMII Receive Data Output[1] (Note 2-2). |
| 13 | RXD0 | Ipu/O | RMII Receive Data Output[0] (Note 2-2). |
| 14 | VDDIO | P | 3.3V, 2.5V, or 1.8V Digital VDD. |
| 15 | CRS_DV/ PHYAD[1:0] | Ipd/O | RMII Mode: Carrier Sense/Receive Data Valid Output. Config. Mode: The pull-up/pull-down value is latched as PHYAD[1:0] at the de-assertion of reset. See the Strapping Options section for details. |
| Pin Number | Pin Name | Type Note 2-1 | Description |
| --------------- | ------------------------ | --------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 16 | REF_CLK / PHYAD [2] | Ipd/O | RMII – 25 MHz Mode: This pin provides the 50 MHz RMII reference clock out put to the MAC. RMII – 50 MHz Mode: This pin is a no connect. For unmanaged mode (power-up default setting), – KSZ8081RNA is in RMII – 25 MHz mode and outputs the 50 MHz RMII ref erence clock on this pin. – KSZ8081RND is in RMII – 50 MHz mode and does not use this pin. Config Mode: The Pull-up/pull-down value is latched as PHYAD [2] at the de-assertion of reset. See Table 2-2 for details. After power-up, both KSZ8081RNA and KSZ8081RND can be programmed to either 25 MHz mode or 50 MHz mode using PHY Register 1Fh Bit [7]. See also XI (Pin 8). |
| 17 | RXER | Ipd/O | RMII Receive Error Output. At the de-assertion of reset, this pin needs to latch in a pull-down value for normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It is better having an external pull-down resistor to avoid MAC side pulls this pin high. |
| 18 | INTRP | Ipu/ Opu | Interrupt Output: Programmable interrupt output. This pin has a weak pull-up, is open drain, and requires an external 1.0 kΩ pull-up resistor. |
| 19 | TXEN | I | RMII Transmit Enable Input. |
| 20 | TXD0 | I | RMII Transmit Data Input [0] (Note 2-3). |
| 21 | TXD1 | I/O | RMII Transmit Data Input [1] (Note 2-3). NAND Tree Mode: NAND Tree output pin. |
| 22 | GND | GND | Ground. |
| LED0/ ANEN_SPEED | Ipu/O | LED Output: Programmable LED0 Output. Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) and Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping Options section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows: LED Mode = [00] Link/Activity | |
| 23 | No Link Link Activity LED Mode = [01] Link No Link Link LED Mode = [10], [11]: Reserved | ||
| Pin Number | Pin Name | Type Note 2-1 | Description |
| 24 | RST# | Ipu | Chip Reset (active-low). |
| Paddle | GND | GND | Ground. |
| Note 2-1 | P = power supply GND = ground I = input O = output I/O = bi-directional Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value). Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). | ||
| Note 2-2 | RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC. | ||
| Note 2-3 | RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC. |
TABLE 2-1: SIGNALS - KSZ8081RNA/RND (CONTINUED)
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC.
Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
The PHYAD [2:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD [2:0] strap-in pin, a shared pin with the RMII CRS_DV and REF_CLK signals, to be latched to the unintended high/low state. In this case an external pullup (4.7 kΩ) or pull-down (1.0 kΩ) should be added on the PHYAD [2:0] strap-in pin to ensure that the intended value is strapped-in correctly.
| Pin Number | Pin Name | Type Note 2-1 | Description |
|---|---|---|---|
| 24 | RST# | Ipu | Chip Reset (active-low). |
| Paddle | GND | GND | Ground. |
TABLE 2-2: STRAP-IN OPTIONS - KSZ8081RNA/RND
Note 2-4 Ipu/O = Input with internal pull-up (see Section 6.0 "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0 "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.
Electrical Characteristics
TA = 25°C. Specification is for packaged product only.
TABLE 6-1: ELECTRICAL CHARACTERISTICS
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
|---|---|---|---|---|---|---|
| Supply Current (VDDIO, VDDA_3.3 = 3.3V), Note 6-1 | ||||||
| 10BASE-T | IDD1_3.3V | — | 41 | — | mA | Full-duplex traffic @ 100% utilization |
| 100BASE-TX | IDD2_3.3V | — | 47 | — | mA | Full-duplex traffic @ 100% utilization |
| EDPD Mode | IDD3_3.3V | — | 20 | — | mA | Ethernet cable disconnected (Reg. 18h.11 = 0) |
| Power-Down Mode | IDD4_3.3V | — | 4 | — | mA | Software power-down (Reg. 0h.11 = 1) |
| CMOS Level Inputs | ||||||
| 2.0 | — | — | VDDIO = 3.3V | |||
| Input High Voltage | VIH | 1.8 | — | — | V | VDDIO = 2.5V |
| 1.3 | — | — | VDDIO = 1.8V | |||
| — | — | 0.8 | V | VDDIO = 3.3V | ||
| Input Low Voltage | VIL | — | — | 0.7 | VDDIO = 2.5V | |
| — | — | 0.5 | VDDIO = 1.8V | |||
| Input Current | IIN | — | — | 10 | μA | VIN = GND ~ VDDIO |
| CMOS Level Outputs | ||||||
| 2.4 | — | — | V | VDDIO = 3.3V | ||
| Output High Voltage | VOH | 2.0 | — | — | VDDIO = 2.5V | |
| 1.5 | — | — | VDDIO = 1.8V | |||
| — | — | 0.4 | VDDIO = 3.3V | |||
| Output Low Voltage | VOL | — | — | 0.4 | V | VDDIO = 2.5V |
| — | — | 0.3 | VDDIO = 1.8V | |||
| Output Tri-State Leakage | IOZ | — | — | 10 | μA | — |
| LED Output | ||||||
| Output Drive Current | ILED | — | 8 | — | mA | LED0 pin |
| All Pull-Up/Pull-Down Pins (including Strapping Pins) | ||||||
| pu | 30 | 45 | 73 | kΩ | VDDIO = 3.3V | |
| Internal Pull-Up Resistance | 39 | 61 | 102 | kΩ | VDDIO = 2.5V | |
| 48 | 99 | 178 | kΩ | VDDIO = 1.8V | ||
| 26 | 43 | 79 | kΩ | VDDIO = 3.3V | ||
| Internal Pull-Down Resistance | pd | 34 | 59 | 113 | kΩ | VDDIO = 2.5V |
| 53 | 99 | 200 | kΩ | VDDIO = 1.8V | ||
| 100BASE-TX Transmit (measured differentially after 1:1 transformer) | ||||||
| Peak Differential Output Voltage | VO | 0.95 | — | 1.05 | V | 100Ω termination across differential output |
| Output Voltage Imbalance | VIMB | — | — | 2 | % | 100Ω termination across differential output |
| Rise/Fall Time | tr/tf | 3 | — | 5 | ns | — |
| Rise/Fall Time Imbalance | — | 0 | — | 0.5 | ns | — |
| Duty Cycle Distortion | — | — | — | ±0.25 | ns | — |
| Overshoot | — | — | — | 5 | % | — |
| Output Jitter | — | — | 0.7 | — | ns | Peak-to-peak |
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
| ------------------------------------------------------------------- | -------- | ------ | ------ | ------ | ------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 10BASE-T Transmit (measured differentially after 1:1 transformer) | ||||||
| Peak Differential Output Voltage | VP | 2.2 | — | 2.8 | V | 100Ω termination across differential output |
| Jitter Added | — | — | — | 3.5 | ns | Peak-to-peak |
| Rise/Fall Time | tr/tf | — | 25 | — | ns | — |
| 10BASE-T Receive | ||||||
| Squelch Threshold | VSQ | — | 400 | — | mV | 5 MHz square wave |
| Transmitter - Drive Setting | ||||||
| Reference Voltage of ISET | VSET | — | 0.65 | — | V | R(ISET) = 6.49 kΩ |
| REF_CLK Output | ||||||
| 50 MHz RMII Clock Output Jitter | — | — | 300 | — | ps | Peak-to-peak. Applies only to RMII - 25 MHz Clock Mode. |
| 100 Mbps Mode - Industrial Applications Parameters | ||||||
| Link Loss Reaction (Indication) Time | tllr | — | 4.4 | — | μs | Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 2. INTRP pin asserts for link-down status change. |
TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Note 6-1 Current consumption is for the single 3.3V supply KSZ8081RNA/RND device only, and includes the transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8081RNA/ RND.
Absolute Maximum Ratings
- (VDDIO, VDDA_3.3) –0.5V to +5.0V
- Input Voltage (all inputs) –0.5V to +5.0V
- Output Voltage (all outputs) –0.5V to +5.0V
- Lead Temperature (soldering, 10s) +260°C
- Storage Temperature (TS)–55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Package Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
FIGURE 12-1: 24-LEAD QFN 4 MM X 4 MM PACKAGE
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| KSZ8081 | Microchip Technology | — |
| KSZ8081MLX | Microchip Technology | 48-pin 7 mm x 7 mm LQFP |
| KSZ8081RNA | Micrel Inc. | — |
| KSZ8081RNA/RND | Microchip Technology | — |
| KSZ8081RNAIA | Microchip Technology | — |
| KSZ8081RNB | Microchip Technology | 32-Pin QFN |
| KSZ8081RND | Micrel Inc. | — |
| KSZ8081RNDCA | Microchip Technology | — |
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