ICE40LP1K-QN84

Part: iCE40™ LP/HX Family (Lattice Semiconductor Corp.)

Type: Field-Programmable Gate Array (FPGA)

Key Specs:

• Logic Cells (LUT4s): 384 to 7,680
• I/O Pins: 10 to 206
• Standby Power: As low as 21 μA
• Process Technology: 40 nm low power CMOS
• Embedded Block RAM: Up to 128 kbits
• Analog PLLs: Up to two per device

Features:

• Flexible Logic Architecture: Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os
• Ultra Low Power Devices: Advanced 40 nm low power process, as low as 21 μA standby power, programmable low swing differential I/Os
• Embedded and

Over Recommended Operating Conditions

• 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled.
• 1. TJ 25°C, f = 1.0 MHz.
• 1. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
• 1. Only applies to IOs in the SPI bank following configuration.
• 1. Some products are clamped to a diode when VIN is larger than VCCIO.
• 1. High current IOs has three sysIO buffers connected together.
• 1. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysIO buffer are connected together.

• Supply Voltage VCC –0.5 V to 1.42 V
• Output Supply Voltage VCCIO, VCC_SPI –0.5 V to 3.60 V
• NVCM Supply Voltage VPP_2V5 –0.5 V to 3.60 V
• PLL Supply Voltage VCCPLL
  –0.5 V to 1.30 V
• I/O Tri-state Voltage Applied –0.5 V to 3.60 V
• Dedicated Input Voltage Applied –0.5 V to 3.60 V
• Storage Temperature (Ambient) –65 °C to 150 °C
• Junction Temperature (TJ) –55 °C to 125 °C

^1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

• 1. Compliance with the Lattice Thermal Management document is required.
• 1. All voltages referenced to GND.
• 1. IOs can support a 200 mV Overshoot above the Recommend Operating Conditions VCCIO (Max) and -200mV Undershoot below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns.

^2. See recommended voltages by I/O standard in subsequent table.

^3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.

^4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.

^5. No PLL available on the iCE40LP384 and iCE40LP640 device.

^6. VCCPLL is tied to VCC internally in packages without PLLs pins.

• 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled.
• 1. TJ 25°C, f = 1.0 MHz.
• 1. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
• 1. Only applies to IOs in the SPI bank following configuration.
• 1. Some products are clamped to a diode when VIN is larger than VCCIO.
• 1. High current IOs has three sysIO buffers connected together.
• 1. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysIO buffer are connected together.