GD25Q16CTJG

Part: GD25Q16C

Type: Serial Flash

Key Specs:

• Memory Size: 16M-bit
• Program/Erase Cycles: Minimum 100,000
• Data Retention: 20-year typical
• Voltage Range: 2.7V to 3.6V
• Clock Frequency: 120MHz for fast read with 30PF load
• Deep Power Down Current: 1uA typical
• Standby Current: 1uA typical
• Page Program Time: 0.6ms typical
• Sector Erase Time: 45ms typical
• Block Erase Time: 0.15/0.25s typical
• Chip Erase Time: 7s typical
• Dual I/O Data Transfer Speed: up to 240Mbits/s
• Quad I/O Data Transfer Speed: up to 480Mbits/s

Features:

• Standard, Dual, Quad SPI
• Fast Program/Erase Speed
• Flexible Architecture: Uniform Sector of 4K-Byte, Uniform Block of 32/64K-Byte
• High Speed Clock Frequency
• Low Power Consumption
• Software/Hardware Write Protection
• Advanced Security Features: 128-Bit Unique ID, 4x256-Byte security registers with OTP locks, Discoverable parameters (SFDP) register
• Single Power Supply Voltage
• Allows XIP (execute in place) Operation
• Continuous Read With 8/16/32/64-Byte Wrap

Applications:

• null

Package:

• SOP8: 150mil
• SOP8: 208mil
• VSOP8: 208mil
• DIP8: 300mil
• USON8: 3*2mm
• USON8: 3*4mm
• USON8: 4*4mm, 0.45 thickness
• WSON8: 6*5mm
• TFBGA-24BALL: 6*4 ball array

• ◆ 16M-bit Serial Flash ◆ Fast Program/Erase Speed -256 Bytes per programmable page -Sector Erase time: 45ms typical
• ◆ Standard, Dual, Quad SPI -Chip Erase time: 7s typical -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ◆Flexible Architecture -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Uniform Sector of 4K-Byte
• ◆ High Speed Clock Frequency -120MHz for fast read with 30PF load ◆ Low Power Consumption -Dual I/O Data transfer up to 240Mbits/s -1uA typical deep power down current -Quad I/O Data transfer up to 480Mbits/s -1uA typical standby current
• ◆ Software/Hardware Write Protection ◆ Advanced Security Features -Write protect all/portion of memory via software -128-Bit Unique ID for each device -Enable/Disable protection with WP# Pin -4x256-Byte security registers with OTP locks -Top/Bottom Block protection -Discoverable parameters (SFDP) register
• ◆ Minimum 100,000 Program/Erase Cycles ◆ Single Power Supply Voltage
• ◆ Data Retention -20-year data retention typical ◆ Package Information

◆ Allows XIP (execute in place) Operation -SOP8 (208mil) -Continuous Read With 8/16/32/64-Byte Wrap -VSOP8 (208mil)

• -2048K-Byte -Page Program time: 0.6ms typical -Block Erase time: 0.15/0.25s typical
  • -Uniform Block of 32/64K-Byte
  • -Full voltage range:2.7~3.6V

  • -SOP8 (150mil) -DIP8 (300mil) -USON8 (3*2mm) -USON8 (3*4mm) -USON8 (4*4mm) -WSON8 (6*5mm)

-TFBGA-24(6*4 ball array)

8.1. POWER-ON TIMING

Table6. Power-Up Timing and Write Inhibit Threshold

8.2. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1(each Byte contains FFH).The Status Register contains 00H (all Status Register bits are 0).

8.3. ABSOLUTE MAXIMUM RATINGS

Figure38. Maximum Negative and Positive Overshoot Waveform

Figure38. Maximum Negative and Positive Overshoot Waveform