DRV832X

DRV832x 6 to 60-V Three-Phase Smart Gate Driver

Manufacturer

Texas Instruments

Overview

Part: DRV832x, Texas Instruments Type: Three-Phase Smart Gate Driver

Key Specs:

  • Operating Voltage Range (Gate Driver): 6 to 60 V
  • Operating Voltage Range (Optional Buck Regulator): 4 to 60 V
  • Peak Source Current: 10 mA to 1 A
  • Peak Sink Current: 20 mA to 2 A
  • Low-Power Sleep Mode Current: 12 μA
  • Linear Voltage Regulator Output: 3.3 V, 30 mA
  • Optional Buck Regulator Output Capability: 0.8 to 60 V, 600 mA
  • Current Sense Amplifier Gain: 5, 10, 20, 40 V/V

Features:

  • Triple Half-Bridge Gate Driver
  • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
  • Smart Gate Drive Architecture
  • Adjustable Slew Rate Control
  • Integrated Gate Driver Power Supplies
  • Supports 100% PWM Duty Cycle
  • High-Side Charge Pump
  • Low-Side Linear Regulator
  • Optional Integrated Buck Regulator (LMR16006X SIMPLE SWITCHER®)
  • Optional Integrated Triple Current Sense Amplifiers (CSAs)
  • Bidirectional or Unidirectional Support for CSAs
  • SPI and Hardware Interface Available
  • 6x, 3x, 1x, and Independent PWM Modes
  • Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
  • Compact QFN Packages and Footprints
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
  • VM Undervoltage Lockout (UVLO)
  • Charge Pump Undervoltage (CPUV)
  • MOSFET Overcurrent Protection (OCP)
  • Gate Driver Fault (GDF)
  • Thermal Warning and Shutdown (OTW/OTSD)
  • Fault Condition Indicator (nFAULT)

Applications:

  • Brushless-DC (BLDC) Motor Modules and PMSM
  • Fans, Pumps, and Servo Drives
  • E-Bikes, E-Scooters, and E-Mobility
  • Cordless Garden and Power Tools, Lawnmowers
  • Cordless Vacuum Cleaners
  • Drones, Robotics, and RC Toys
  • Industrial and Logistics Robots

Package:

  • DRV8320: WQFN (32): 5.00 mm × 5.00 mm
  • DRV8320R: VQFN (40): 6.00 mm × 6.00 mm
  • DRV8323: WQFN (40): 6.00 mm × 6.00 mm
  • DRV8323R: VQFN (48): 7.00 mm × 7.00 mm

Features

  • Triple Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
  • Smart Gate Drive Architecture
    • Adjustable Slew Rate Control
    • 10-mA to 1-A Peak Source Current
    • 20-mA to 2-A Peak Sink Current
  • Integrated Gate Driver Power Supplies
    • Supports 100% PWM Duty Cycle
    • High-Side Charge Pump
    • Low-Side Linear Regulator
  • 6 to 60-V Operating Voltage Range
  • Optional Integrated Buck Regulator
    • LMR16006X SIMPLE SWITCHER®
    • 4 to 60-V Operating Voltage Range
    • 0.8 to 60-V, 600-mA Output Capability
  • Optional Integrated Triple Current Sense Amplifiers (CSAs)
    • Adjustable Gain (5, 10, 20, 40 V/V)
    • Bidirectional or Unidirectional Support
  • SPI and Hardware Interface Available
  • 6x, 3x, 1x, and Independent PWM Modes
  • Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
  • Low-Power Sleep Mode (12 μA)
  • Linear Voltage Regulator, 3.3 V, 30 mA
  • Compact QFN Packages and Footprints
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • VM Undervoltage Lockout (UVLO)
    • Charge Pump Undervoltage (CPUV)
    • MOSFET Overcurrent Protection (OCP)
    • Gate Driver Fault (GDF)
    • Thermal Warning and Shutdown (OTW/OTSD)
    • Fault Condition Indicator (nFAULT)

Applications

  • Brushless-DC (BLDC) Motor Modules and PMSM
  • Fans, Pumps, and Servo Drives
  • E-Bikes, E-Scooters, and E-Mobility
  • Cordless Garden and Power Tools, Lawnmowers
  • Cordless Vacuum Cleaners
  • Drones, Robotics, and RC Toys
  • Industrial and Logistics Robots

3 Description

The DRV832x family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The DRV832x generates the correct gate drive voltages using an integrated charge pump for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV832x can operate from a single power supply and supports a wide input supply range of 6 to 60 V for the gate driver and 4 to 60 V for the optional buck regulator.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8323 and DRV8323R devices integrate three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage. The DRV8320R and DRV8323R devices integrate a 600-mA buck regulator.

A low-power sleep mode is provided to achieve low quiescent current draw by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for SPI device variants.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
DRV8320WQFN (32)5.00 mm × 5.00 mm
DRV8320RVQFN (40)6.00 mm × 6.00 mm
DRV8323WQFN (40)6.00 mm × 6.00 mm
DRV8323RVQFN (48)7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

Copyright © 2017, Texas Instruments Incorporated

1 Features......................................................................1

8.6 Register Maps..................................................... 53

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Changes from Original (February 2017) to Revision APage
•Changed the test condition for the IBIAS parameter in the Electrical Characteristics table16
•Changed the GHx values in the 3x PWM Mode Truth Table31
•Changed the calibration description and added auto calibration feature description44

Device Comparison Table

DEVICEVARIANT (1)CURRENT SENSE
AMPLIFIERS		BUCK REGULATOR (1)INTERFACE (1)
DRV8320DRV8320HNoneHardware
DRV0320DRV8320S0NoneSPI
DD/0000DDRV8320RHU600 m AHardware
DRV8320RDRV8320RS600 mASPI
DDV0000DRV8323HNamaHardware
DRV8323DRV8323S3NoneSPI
DRV8323RDRV8323RHა600 m AHardware
DRV8323RS600 mASPI

(1) For more information on the device name and device options, see the Device Nomenclature section. For additional details, see the Architecture for Brushless-DC Gate Drive Systems application report.

Pin Configuration

Pin Functions—32-Pin DRV8320 Devices

  • NAME
  • NAIVIE
  • AGND
  • CPH
  • CPL
  • DVDD
  • ENABLE
  • GHA
  • GHB
  • GHC

PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

Pin Functions—32-Pin DRV8320 Devices(continued)

  • NAME
  • GLA
  • GLB
  • GLC
  • IDRIVE
  • INHA
  • INHB
  • INHC
  • INLA
  • INLB
  • INLC
  • MODE
  • NC
  • nFAULT
  • nSCS
  • PGND
  • SCLK
  • SDI
  • SDO
  • SHA
  • SHB
  • SHC
  • SLA
  • SLB
  • SLC
  • VCP
  • VDRAIN
  • VDS
  • VM
  • Thermal Pad

DRV8320RH RHA Package 40-Pin VQFN With Exposed Thermal Pad Top View

DRV8320RS RHA Package 40-Pin VQFN With Exposed Thermal Pad Top View

Pin Functions-40-Pin DRV8320R Devices

PIN
NO.
NAMEDRV8320RH
AGND26
BGND34
CB35
CPH3
CPL2
DVDD27
ENABLE25
FB40
GHA7
GHB14
GHC15
GLA9
GLB12
GLC17
GND19
IDRIVE22
INHA28
INHB30
INHC32
INLA29
INLB31
INLC33
MODE21
NC24
NC37
nFAULT20

Pin Functions—40-Pin DRV8320R Devices (continued)

  • NAME
  • IVAIVIE
  • nSCS
  • nSHDN
  • PGND
  • SCLK
  • SDI
  • SDO
  • SHA
  • SHB
  • SHC
  • SLA
  • SLB
  • SLC
  • SW
  • VCP
  • VDRAIN
  • VDS
  • VIN
  • VM 5 5
  • Thermal F

DRV8323H RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View

INHC INLB INHB DVD AGN PGN INLA NHA CAL Ĭ 35 34 33 32 CPL Ĺ. ENABLE GAIN _______________________________________ VCP ___3 VDS IDRIVE 27 VM ے 4 ر MODE VDRAIN 5 Therma Pad GHA nFAULT _______________________________________ VREF GLA 23 . . 8 SOA SPA ____ 9 22 SOB ______10 SNA 21 SOC 12 13 4 15 16 17 19 8 20 пппп GLC SNC Not to scale

DRV8323S RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View

Pin Functions—40-Pin DRV8323 Devices

  • NAME NO.
  • NAWIE
  • AGND
  • CAL
  • CPH
  • (1) PW

Pin Functions—40-Pin DRV8323 Devices(continued)

  • NAME
  • CPL
  • DVDD
  • ENABLE
  • GAIN
  • GHA
  • GHB
  • GHC
  • GLA
  • GLB
  • GLC
  • IDRIVE
  • INHA
  • INHB
  • INHC
  • INLA
  • INLB
  • INLC
  • MODE
  • nFAULT
  • nSCS
  • PGND
  • SCLK
  • SDI
  • SDO
  • SHA
  • SHB
  • SHC
  • SNA
  • SNB
  • SNC
  • SOA
  • SOB
  • SOC
  • SPA
  • SPB
  • SPC
  • VCP
  • VDRAIN
  • VDS
  • VM
  • VREF
  • Thermal Pad

DRV8323RH RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

DRV8323RS RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

Pin Functions—48-Pin DRV8323R Devices

PIN
NAMEN
NAMEDRV8323RH
AGND35
BGND43
CAL34
CB44
CPH4
CPL3
DGND27
DVDD36
ENABLE33
FB1
GAIN32
GHA8
GHB17
GHC18
GLA10
GLB15
GLC20
IDRIVE30
INHA37
INHB39
INHC41
INLA38
INLB40
INLC42
MODE29
NC46
nFAULT28

Electrical Characteristics

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (DVDD, VCP, VM)
IVMVM operating supply currentVVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V10.514mA
ENABLE = 0 V, VVM = 24 V, TA = 25°C1220
IVMQVM sleep mode supply currentENABLE = 0 V, VVM = 24 V, TA = 125°C(1)50μA
tRST(1)Reset pulse timeENABLE = 0 V period to reset faults840μs
tWAKETurnon timeVVM > VUVLO, ENABLE = 3.3 V to outputs ready1ms
tSLEEPTurnoff timeENABLE = 0 V to device sleep mode1ms
VDVDDDVDD regulator voltageIDVDD = 0 to 30 mA33.33.6V
VVM = 13 V, IVCP = 0 to 25 mA8.41112.5
VVCP operating voltageVVM = 10 V, IVCP = 0 to 20 mA6.3910
VCPwith respect to VMVVM = 8 V, IVCP = 0 to 15 mA5.478V
VVM = 6 V, IVCP = 0 to 10 mA456
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VILInput logic low voltage00.8V
VIHInput logic high voltage1.55.5V
VHYSInput logic hysteresis100mV
IILInput logic low currentVVIN = 0 V–55μA
IIHInput logic high currentVVIN = 5 V5070μA
RPDPulldown resistanceTo AGND100kΩ
tPDPropagation delayINHx/INLx transition to GHx/GLx transition150ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1Input mode 1 voltageTied to AGND0V
VI2Input mode 2 voltage45 kΩ ± 5% to tied AGND1.2V
VI3Input mode 3 voltageHi-Z2V
VI4Input mode 4 voltageTied to DVDD3.3V
RPUPullup resistanceInternal pullup to DVDD50kΩ
RPDPulldown resistanceInternal pulldown to AGND84kΩ
SEVEN-LEVEL H/WINPUTS (IDRIVE, VDS)
VI1Input mode 1 voltageTied to AGND0V
VI2Input mode 2 voltage18 kΩ ± 5% tied to AGND0.5V
VI3Input mode 3 voltage75 kΩ ± 5% tied to AGND1.1V
VI4Input mode 4 voltageHi-Z1.65V
VI5Input mode 5 voltage75 kΩ ± 5% tied to DVDD2.2V
VI6Input mode 6 voltage18 kΩ ± 5% tied to DVDD2.8V
VI7Input mode 7 voltageTied to DVDD3.3V
RPUPullup resistanceInternal pullup to DVDD73kΩ
RPDPulldown resistanceInternal pulldown to AGND73kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOLOutput logic low voltageIO = 5 mA0.1V
IOZOutput high impedance leakageVO = 5 V–22μA

(1) Specified by design and characterization data

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
GATE DRIVERS (GHx, GLx)
VVM = 13 V, IVCP = 0 to 25 mA8.41112.5
V (1)High-side gate drivve voltageV VM = 10 , I VCP = 0 to 20 mA6.3910V
V GSH (1)with respect to SH(VVM = 8 V, IVCP = 0 to 15 mA5.478V
VVM = 6 V, IVCP = 0 to 10 mA8.4 11 12.5
6.3 9 10
VVM = 12 V, IVGLS = 0 to 25 mA91112
V (1)Low-side gate drivee voltageV VM = 10 V, I VGLS = 0 to 20 mA7.5910.,
V GSL (1)with respect to PGNDVVM = 8 V, IVGLS = 0 to 15 mA5.578V
VVM = 6 V, IVGLS = 0 to 10 mA456
DEAD_TIME = 00b50
DEAD_TIME = 01b100
t DEADGate dri v e
dead time		SPI DeviceDEAD_TIME = 10b200ns
dead timeDEAD_TIME = 11b400
H/W Device=100
TDRIVE = 00b
TDRIVE = 01b
t DRIVEPeak currentSPI DeviceTDRIVE = 10bns
DRIVEgate drive timeTDRIVE = 11b
H/W DeviceTENUE TIE
TWW BOVIOUIDRIVEP HSorIDRIVEP LS = 0000b
IDRIVEP_HS or IDRIVEP_LS = 0001b
IDRIVEP_HS or IDRIVEP_LS = 0010b
IDRIVEP HS or IDRIVEP LS = 0011b
IDRIVEP HS or IDRIVEP LS = 0100b
IDRIVEP_HS or IDRIVEP_LS = 0101b
IDRIVEP HS or IDRIVEP LS = 0110b
IDRIVEP_HS or IDRIVEP_LS = 0111b
SPI Device
IDRIVEP_HS or IDRIVEP_LS = 1000b
IDRIVEP_HS or IDRIVEP_LS = 1001b
Peak sourceIDRIVEP_HS or IDRIVEP_LS = 1010b^
I DRIVEPgate currentIDRIVEP_HS or IDRIVEP_LS = 1011bmA
IDRIVEP_HS or IDRIVEP_LS = 1100b
IDRIVEP_HS or IDRIVEP_LS = 1101b
IDRIVEP_HS or IDRIVEP_LS = 1110b
IDRIVEP_HS or IDRIVEP_LS = 1111b
IDRIVE = Tied to AGND
IDRIVE = 18 kΩ ± 5% tied to AGND
IDRIVE = 75 kΩ ± 5% tied to AGND
H/W Device120
ıIDRIVE = 75 kΩ ± 5% tied to DVDD260
IDRIVE = 18 kΩ ± 5% tied to DVDD570
IDRIVE = Tied to DVDD1000

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IDRIVEN_HS or IDRIVEN_LS = 0000b20
IDRIVEN_HS or IDRIVEN_LS = 0001b60
IDRIVEN_HS or IDRIVEN_LS = 0010b120
IDRIVEN_HS or IDRIVEN_LS = 0011b160
IDRIVEN_HS or IDRIVEN_LS = 0100b240
IDRIVEN_HS or IDRIVEN_LS = 0101b280
IDRIVEN_HS or IDRIVEN_LS = 0110b340
IDRIVEN_HS or IDRIVEN_LS = 0111b380
SPI DeviceIDRIVEN_HS or IDRIVEN_LS = 1000b520
IDRIVEN_HS or IDRIVEN_LS = 1001b660
IDRIVEN_HS or IDRIVEN_LS = 1010b740
IDRIVENPeak sinkIDRIVEN_HS or IDRIVEN_LS = 1011b880mA
gate currentIDRIVEN_HS or IDRIVEN_LS = 1100b1140
IDRIVEN_HS or IDRIVEN_LS = 1101b1360
IDRIVEN_HS or IDRIVEN_LS = 1110b1640
IDRIVEN_HS or IDRIVEN_LS = 1111b
IDRIVE = Tied to AGND
IDRIVE = 18 kΩ ± 5% tied to AGND
IDRIVE = 75 kΩ ± 5% tied to AGND
H/W DeviceIDRIVE = Hi-Z
IDRIVE = 75 kΩ ± 5% tied to DVDD2000
20
60
120
240
520
1140
2000
10
50
2
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
IHOLDGate holding currentSource current after tDRIVEmA
Sink current after tDRIVE
ISTRONGGate strong pulldown currentGHx to SHx and GLx to PGNDA
ROFFGate hold off resistorGHx to SHx and GLx to PGND150kΩ
CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b4.8555.15
CSA_GAIN = 01b9.71010.3
SPI DeviceCSA_GAIN = 10b19.42020.6
CSA_GAIN = 11b38.84041.2
GCSAAmplifier gainGAIN = Tied to AGND4.8555.15V/V
GAIN = 47 kΩ ± 5% tied to AGND9.71010.3
H/W DeviceGAIN = Hi-Z19.42020.6
GAIN = Tied to DVDD38.84041.2
VO_STEP = 0.5 V, GCSA = 5 V/V150
VO_STEP = 0.5 V, GCSA = 10 V/V300
tSET(1)Settling time to ±1%VO_STEP = 0.5 V, GVSA = 20 V/V600ns
VO_STEP = 0.5 V, GCSA = 40 V/V1200
VCOM
Common mode input range–0.150.15V
VDIFF
VOFF		Differential mode inputrange–0.30.3V
Input offset errorVSP = VSN = 0 V, CAL = 3.3 V, VREF = 3.3 V–44mV
10μV/°C
VDRIFT(1)Drift offsetVSP = VSN = 0 VVVREF

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0bVVREF – 0.3
VBIASSOx output voltage
bias		SPI DeviceVSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1bVVREF / 2V
H/W DeviceVSP = VSN = 0 V, CAL = 3.3 VVVREF / 2
IBIASSPx/SNx input biascurrentVREF_DIV = 1b100μA
VSLEW(1)SOx output slew rate60-pF loadV/μs
IVREFVREF input currentVVREF = 5 V23mA
UGB(1)Unity gain bandwidth60-pF load1MHz
PROTECTION CIRCUITS
VM falling, UVLO report5.45.65.8
VUVLOVM undervoltage lockoutVM rising, UVLO recovery5.65.86V
VUVLO_HYSVM undervoltage hysteresisRising to falling threshold200mV
tUVLO_DEGVM undervoltage deglitch timeVM falling, UVLO report10μs
VCPUVCharge pump undervoltage
lockout		VCP falling, CPUV reportVVM + 2.8V
Positive clamping voltage1516.518
VGS_CLAMPHigh-side gate clampNegative clamping voltage–0.7V
VDS_LVL = 0000b0.06
VDS_LVL = 0001b0.13
VDS_LVL = 0010b
VDS_LVL = 0011b0.2610
0.2
0.6
0.68
0.94
1.3
1.5
1.7
1.88
0.06
0.13
0.26
0.6
1.13
1.88
Disabled
2
4
6
8
4
VDS_LVL = 0100b0.31
VDS_LVL = 0101b0.45
VDS_LVL = 0110b0.53
VDS_LVL = 0111b
SPI DeviceVDS_LVL = 1000b
VDS_LVL = 1001b0.75
VDS_LVL = 1010b
VVDS_OCPVDS overcurrentVDS_LVL = 1011b1.13V
trip voltageVDS_LVL = 1100b
VDS_LVL = 1101b
VDS_LVL = 1110b
VDS_LVL = 1111b
VDS = Tied to AGND
VDS = 18 kΩ ± 5% tied to AGND
VDS = 75 kΩ ± 5% tied to AGND
H/W DeviceVDS = Hi-Z
VDS = 75 kΩ ± 5% tied to DVDD
VDS = 18 kΩ ± 5% tied to DVDD
VDS = Tied to DVDD
OCP_DEG = 00b
OCP_DEG = 01b
VDS and VSENSE
overcurrent		SPI Device
tOCP_DEGdeglitch timeOCP_DEG = 10bμs
H/W DeviceOCP_DEG = 11b
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SEN_LVL = 00b0.25
SEN_LVL = 01b0.5
VSEN_OCPVSENSE overcurrent
trip voltage		SPI DeviceSEN_LVL = 10b0.75V
SEN_LVL = 11b1
H/W Device1
TRETRY = 0b4ms
tRETRYOvercurrent retry
time		SPI DeviceTRETRY = 1b50μs
H/W Device4ms
TOTW(1)Thermal warning temperatureDie temperature, TJ130150165°C
TOTSD (1)Thermal shutdown temperatureDie temperature, TJ150170185°C
THYS(1)Thermal hysteresisDie temperature, TJ20°C
BUCK REGULATOR SUPPLY (VIN)
InSHDNShutdown supply currentVnSHDN = 0 V13μA
IQOperating quiescent currentVVIN = 12 V, no load; not switching28μA
VIN undervoltage lockoutVIN Rising4
VVIN_UVLOthresholdVIN Falling3V
BUCK REGULATOR SHUTDOWN (nSHDN)
VnSHDN_THRising nSHDN threshold1.051.251.38V
VnSHDN = 2.3 V–4.2
InSHDNInput currentVnSHDN = 0.9 V–1μA
InSHDN_HYSHysteresis current–3μA
BUCK REGULATOR HIGH-SIDE MOSFET
RDS_ONMOSFET on resistanceVVIN = 12 V, VCB to VSW = 5.8 V, TA = 25°C900mΩ
BUCK REGULATOR VOLTAGE REFERENCE (FB)
VFBFeedback voltage0.7470.7650.782V
BUCK REGULATOR CURRENT LIMIT
VVIN = 12 V, TA = 25°C1200
ILIMITPeak current limit1700mA
BUCK REGULATOR SWITCHING (SW)
fSWSwitching frequency595700805kHz
DMAXMaximum duty cycle96%
BUCK REGULATOR THERMAL SHUTDOWN
(1)
TSHDN		Thermal shutdown threshold170°C
THYS(1)Thermal shutdown hysteresis10°C

Absolute Maximum Ratings

at TA = –40°C to +125°C (unless otherw ise noted)(1)

MINMAXUNIT
GATE DRIVER
Power supply pin voltage (VM)–0.365V
Voltage differential between ground pins(AGND, BGND, DGND, PGND)–0.30.3V
MOSFET drain sense pin voltage (VDRAIN)–0.365V
Charge pump pin voltage (CPH, VCP)–0.3VVM + 13.5V
Charge pump negative-switching pin voltage (CPL)–0.3VVMV
Internal logic regulator pin voltage (DVDD)–0.33.8V
Digital pin voltage (CAL, ENABLE,GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS,
SCLK, SDI, SDO, VDS)		–0.35.75V
Continuoushigh-side gate drive pin voltage (GHx)–5(2)VVCP + 0.5V
Transient 200-nshigh-side gate drive pin voltage (GHx)–7VVCP + 0.5V
High-side gate drive pin voltage with respect to SHx (GHx)–0.313.5V
Continuoushigh-side source sense pin voltage (SHx)–5(2)VVM + 5V
Transient 200-nshigh-side source sense pin voltage (SHx)–7VVM + 7V
Continuouslow-side gate drive pin voltage (GLx)–0.513.5V
Gate drive pin source current (GHx, GLx)Internally limitedA
Gate drive pin sinkcurrent (GHx, GLx)Internally limitedA
Continuouslow-side source sense pin voltage (SLx)–11V
Transient 200-nslow-side source sense pin voltage (SLx)–33V
Continuousinput pin voltage (SNx, SPx)–11V
Transient 200-nsinput pin voltage (SNx, SPx)–33V
Reference input pin voltage (VREF)–0.35.75V
output pin voltage (SOx)–0.3VVREF + 0.3V
BUCK REGULATOR
Power supply pin voltage (VIN)–0.365V
Shutdown control pin voltage (nSHDN)–0.3VVINV
Voltage feedbackpin voltage (FB)–0.37V
Bootstrap pin voltagewith respect to SW(CB)–0.37V
Switching node pin voltage (SW)–0.3VVINV
Switching node pin voltage lessthan 30-nstransients(SW)–2VVINV
DRV832x
Operating junction temperature, TJ–40150°C
Storage temperature, Tstg–65150°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditionsbeyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditionsfor extended periodsmay affect device reliability.

Recommended Operating Conditions

at TA = -40 °C to +125°C (unless otherwise noted)

MINMAXUNIT
GATE DRIVIER•
VVMPower supply voltage (VM)660V
VıInput voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)05.5V
f PWMApplied PWM signal (INHx, INLx)0200 (1)kHz
I GATE_HSHigh-side average gate drive current (GHx)025 (1)mA
I GATE_LSLow-side average gate drive current (GLx)025 (1)mA
I DVDDExternal load current (DVDD)030(1)mA
VVREFReference voltage input (VREF)35.5V
I SOoutput current (SOx)05mA
V ODOpen drain pullup voltage (nFAULT, SDO)05.5V
IODOpen drain output current (nFAULT, SDO)05mA
BUCK REGIJLATOR
V VINPower supply voltage (VIN)460V
VnSHDNShutdown control input voltage (nSHDN)060V
DRV832x
T AOperating ambient temperature-40125°C

(1) Power dissipation and thermal limits must be observed

7.4 Thermal Information

DRV/832x
THERMAL METRIC(1)RTV
(WQFN)		RHA
(VQFN)		RTA
(WQFN)
32 PINS40 PINS40 PINS
Rθ JAJunction-to-ambient thermal resistance32.930.132.1
Rθ JC(top)Junction-to-case (top) thermal resistance15.816.711
Rθ JBJunction-to-board thermal resistance6.89.97.1
ψυτJunction-to-top characterization parameter0.20.50.1
ΨЈBJunction-to-board characterization parameter6.89.97.1
Rθ JC(bot)Junction-to-case (bottom) thermal resistance2.12.22.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Thermal Information

Related Variants

The following components are covered by the same datasheet.

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DRV8323HRTAT.ATexas Instruments—
DRV8323RTexas Instruments—
DRV8323RHTexas Instruments—
DRV8323RSTexas Instruments—
DRV8323STexas Instruments—
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DRV8323SRTATTexas Instruments—
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