DRV8323/PART

Three-Phase Smart Gate Driver

The DRV8323/PART is a three-phase smart gate driver from Texas Instruments. View the full DRV8323/PART datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

DRV8323/PART shares its datasheet with DRV8323RS, whose page lists every part number it covers.

Official DRV8323/PART datasheet (PDF) — the source this page was extracted from.

Manufacturer

Texas Instruments

DRV8323/PART Key Specifications

Parameter	Value
Gate drive peak current	10 mA to 1 A source, 20 mA to 2 A sink
Current sense amplifier gain	adjustable 5, 10, 20, 40 V/V (bidirectional or unidirectional)
Buck regulator output	0.8 to 60 V, 600 mA
Sleep mode current	12 μA (typ)
DVDD linear regulator	3.3 V, 30 mA
Logic input support	1.8 V, 3.3 V, 5 V
VREF range for current sense amplifiers	3–5.5 V
PWM modes	6x, 3x, 1x, and independent

DRV8323/PART Overview

Part: DRV8323RS — Texas Instruments

Type: Three-Phase Smart Gate Driver with integrated current sense amplifiers and buck regulator (SPI interface)

Description: 6–60 V three-phase smart gate driver with up to 1 A source / 2 A sink peak gate current, three integrated low-side current sense amplifiers, a 600 mA integrated buck regulator, and SPI interface.

Operating Conditions:

Gate driver supply voltage (VM): 6–60 V
Buck regulator supply voltage (VIN): 4–60 V
Operating ambient temperature: -40 to 125 °C
Applied PWM frequency (INHx, INLx): up to 200 kHz
Average gate drive current (GHx/GLx): up to 25 mA each; DVDD external load up to 30 mA

Absolute Maximum Ratings:

Max supply voltage (VM): 65 V
Max buck regulator supply voltage (VIN): 65 V
Max junction temperature: 150 °C
Storage temperature: -65 to 150 °C

Key Specs:

Gate drive peak current: 10 mA to 1 A source, 20 mA to 2 A sink
Current sense amplifier gain: adjustable 5, 10, 20, 40 V/V (bidirectional or unidirectional)
Buck regulator output: 0.8 to 60 V, 600 mA
Sleep mode current: 12 μA (typ)
DVDD linear regulator: 3.3 V, 30 mA
Logic input support: 1.8 V, 3.3 V, 5 V
VREF range for current sense amplifiers: 3–5.5 V
PWM modes: 6x, 3x, 1x, and independent

Features:

Triple half-bridge gate driver for 3 high-side and 3 low-side N-channel MOSFETs
Smart Gate Drive architecture with adjustable slew rate control
Integrated high-side charge pump and low-side linear regulator; supports 100% PWM duty cycle
Integrated LMR16006X SIMPLE SWITCHER buck regulator
Integrated triple low-side current sense amplifiers
SPI configuration interface
Protection: VM UVLO, charge pump UV, MOSFET overcurrent, gate driver fault, thermal warning/shutdown
nFAULT fault indicator

Applications:

Brushless-DC (BLDC) and PMSM motor modules
Fans, pumps, and servo drives
E-bikes, e-scooters, and e-mobility
Cordless garden and power tools, lawnmowers
Cordless vacuum cleaners
Drones, robotics, and RC toys
Industrial and logistics robots

Package:

VQFN (48), 7.00 mm × 7.00 mm (DRV8323R family)

DRV8323/PART Features

Triple Half-Bridge Gate Driver
-Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
Smart Gate Drive Architecture
-Adjustable Slew Rate Control
-10-mA to 1-A Peak Source Current
-20-mA to 2-A Peak Sink Current
Integrated Gate Driver Power Supplies
-Supports 100% PWM Duty Cycle
-High-Side Charge Pump
-Low-Side Linear Regulator
6 to 60-V Operating Voltage Range
Optional Integrated DC/DC Buck Regulator
-LMR16006X SIMPLE SWITCHER ®
-4 to 60-V Operating Voltage Range
-0.8 to 60-V, 600-mA Output Capability
Optional Integrated Triple Low-Side Current Sense Amplifiers (CSAs)
-Adjustable Gain (5, 10, 20, 40 V/V)
-Bidirectional or Unidirectional Support
SPI and Hardware Interface Available
6x, 3x, 1x, and Independent PWM Modes
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Low-Power Sleep Mode (12 μA)
Linear Voltage Regulator, 3.3 V, 30 mA
Compact QFN Packages and Footprints
Efficient System Design With Power Blocks
Integrated Protection Features
-VM Undervoltage Lockout (UVLO)
-Charge Pump Undervoltage (CPUV)
-MOSFET Overcurrent Protection (OCP)
-Gate Driver Fault (GDF)
-Thermal Warning and Shutdown (OTW/OTSD)
-Fault Condition Indicator (nFAULT)

DRV8323/PART Applications

Brushless-DC (BLDC) Motor Modules and PMSM
Fans, Pumps, and Servo Drives
E-Bikes, E-Scooters, and E-Mobility
Cordless Garden and Power Tools, Lawnmowers
Cordless Vacuum Cleaners
Drones, Robotics, and RC Toys
Industrial and Logistics Robots

DRV8323/PART Pin Configuration

Figure 6-1. DRV8320H RTV Package 32-Pin WQFN With Exposed Thermal Pad Top View

Figure 6-2. DRV8320S RTV Package 32-Pin WQFN With Exposed Thermal Pad Top View

Table 6-1. Pin Functions-32-Pin DRV8320 Devices

PIN - NAME	PIN - NO. - DRV8320H	PIN - NO. - DRV8320S	TYPE (1)
AGND	23	23	PWR	Device analog ground. Connect to system ground. AGND must be connected to PGND externally.
CPH	1	1	PWR	Charge pump switching node. Connect an X5R or X7R, 47nF, VM-rated ceramic capacitor between the CPH and CPL pins. For example, in a 24V system the capacitor should be rated 50V (2x margin).
CPL	32	32	PWR	Charge pump switching node. Connect an X5R or X7R, 47nF, VM-rated ceramic capacitor between the CPH and CPL pins. For example, in a 24V system the capacitor should be rated 50V (2x margin).
DVDD	24	24	PWR	3.3V internal regulator output. Connect an X5R or X7R, 1μF, 6.3V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE	22	22	I	Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40μs pulse can be used to reset fault conditions without entering sleep mode.
GHA	5	5	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB	12	12	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC	13	13	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA	7	7	O	Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB	10	10	O	Low-side gate driver output. Connect to the gate of the low-side power MOSFET.

DRV8323/PART Electrical Characteristics

at T A = -40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)

PARAMETER	PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)	POWER SUPPLIES (DVDD, VCP, VM)
I VM	VM operating supply current	V VM = 24V, ENABLE = 3.3V, INHx/INLx = 0	10.5	14	mA
I	VM sleep mode supply current	ENABLE = 0V, V VM = 24V, T A = 25°C	12	20	μA
VMQ		ENABLE = 0V, V VM = 24V, T A = 125°C (1)		50 40	μs
t RST (1) t WAKE	Reset pulse time Wake up time	ENABLE = low period to reset faults V VM > V UVLO , ENABLE = 3.3V to outputs ready		1	ms
t SLEEP	Sleep time	ENABLE = 0V to device sleep mode		1	ms
V DVDD	DVDD regulator voltage	I DVDD = 0 to 30mA	3.3	3.6	V
	VCP operating voltage with respect to VM	V VM = 13V, I VCP = 0 to 25mA	11	12.5
V VCP		V VM = 10V, I VCP = 0 to 20mA V VM = 8V, I VCP = 0 to 15mA V VM = 6V, I VCP = 0 to 10mA	9 7 5	10 8 6	V
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)	LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
V IL	Input logic low voltage			0.8	V
V IH	Input logic high voltage			5.5	V
V HYS	Input logic hysteresis		100		mV
I IL	Input logic low current	V VIN = 0V		5	μA
I IH	Input logic high current	V VIN = 5V	50	70	μA
R PD	Pulldown resistance	To AGND	100		kΩ
t PD	Propagation delay	INHx/INLx transition to GHx/GLx transition	150		ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)
V I1	Input mode 1 voltage	Tied to AGND	0		V
V I2	Input mode 2 voltage	45kΩ ± 5% tied to AGND	1.2		V
V I3	Input mode 3 voltage	Hi-Z	2		V
V I4	Input mode 4 voltage	Tied to DVDD	3.3		V
R PU	Pullup resistance	Internal pullup to DVDD	50		kΩ
R PD	Pulldown resistance	Internal pulldown to AGND	84		kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
V I1	Input mode 1 voltage	Tied to AGND	0		V
V I2	Input mode 2 voltage	18kΩ ± 5% tied to AGND	0.5		V
V I3	Input mode 3 voltage	75kΩ ± 5% tied to AGND	1.1		V
V I4	Input mode 4 voltage	Hi-Z	1.65		V
V I5	Input mode 5 voltage	75kΩ ± 5% tied to DVDD	2.2		V
V I6	Input mode 6 voltage	18kΩ ± 5% tied to DVDD	2.8		V
V I7	Input mode 7 voltage	Tied to DVDD	3.3		V
R PU	Pullup resistance	Internal pullup to DVDD	73		kΩ
R PD	Pulldown resistance	Internal pulldown to AGND	73		kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)
V OL	Output logic low voltage	I O = 5mA		0.1	V
I OZ	Output high impedance leakage	V O = 5V		2	μA

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at T A = -40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
		V VM = 13V, I VCP = 0 to 25mA	8.4	11	12.5
V GSH (1)	High-side gate drive voltage	V VM = 10V, I VCP = 0 to 20mA	6.3	9	10	V
		V VM = 8V, I VCP = 0 to 15mA	5.4	7	8
		V VM = 6V, I VCP = 0 to 10mA	4	5	6
V (1)		V VM = 12V, I VGLS = 0 to 25mA	9	11	12
		V VM = 10V, I VGLS = 0 to 20mA	7.5	9	10
GSL		V VM = 8V, I VGLS = 0 to 15mA	5.5	7	8	V
		V VM = 6V, I VGLS = 0 to 10mA DEAD_TIME = 00b DEAD_TIME = 01b	4	5 50 100	6
t DEAD		DEAD_TIME = 10b DEAD_TIME = 11b TDRIVE = 00b TDRIVE = 01b		200 400 100 500 1000		ns
t DRIVE		TDRIVE = 10b = 11b TDRIVE IDRIVEP_HS or IDRIVEP_LS = 0000b IDRIVEP_HS or IDRIVEP_LS = 0010b IDRIVEP_HS or IDRIVEP_LS = 0011b IDRIVEP_HS or IDRIVEP_LS = 0100b IDRIVEP_HS or IDRIVEP_LS = 0101b IDRIVEP_HS or IDRIVEP_LS = 0110b IDRIVEP_HS or IDRIVEP_LS = 0111b IDRIVEP_HS or IDRIVEP_LS = 1000b IDRIVEP_HS or IDRIVEP_LS = 1001b IDRIVEP_HS or IDRIVEP_LS = 1010b		2000 4000 4000 10 60 80 120 140 170 190 260 330 370		ns
I DRIVEP		IDRIVEP_HS or IDRIVEP_LS = 1011b IDRIVEP_HS or IDRIVEP_LS = 1100b IDRIVEP_HS or IDRIVEP_LS = 1101b IDRIVEP_HS or IDRIVEP_LS = 1110b IDRIVEP_HS or IDRIVEP_LS = 1111b IDRIVE = Tied to AGND IDRIVE = 18kΩ ± 5% tied to AGND IDRIVE = 75kΩ ± 5% tied to AGND IDRIVE = Hi-Z IDRIVE = 75kΩ ± 5% tied to DVDD IDRIVE = 18kΩ ± 5% tied to DVDD IDRIVE = Tied to DVDD		440 570 680 820 1000 10 30 60 120 260 570 1000		mA

at T A = -40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)

	PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
I DRIVEN	SPI Device	IDRIVEN_HS or IDRIVEN_LS = 0000b IDRIVEN_HS or IDRIVEN_LS = 0001b IDRIVEN_HS or IDRIVEN_LS = 0010b IDRIVEN_HS or IDRIVEN_LS = 0011b IDRIVEN_HS or IDRIVEN_LS = 0100b IDRIVEN_HS or IDRIVEN_LS = 0101b IDRIVEN_HS or IDRIVEN_LS = 0110b IDRIVEN_HS or IDRIVEN_LS = 0111b IDRIVEN_HS or IDRIVEN_LS = 1000b IDRIVEN_HS or IDRIVEN_LS = 1001b IDRIVEN_HS or IDRIVEN_LS = 1010b	20 60 120 160 240 280 340 380 520 660 740
	Peak sink gate current H/W Device	IDRIVEN_HS or IDRIVEN_LS = 1011b IDRIVEN_HS or IDRIVEN_LS = 1100b IDRIVEN_HS or IDRIVEN_LS = 1101b IDRIVEN_HS or IDRIVEN_LS = 1110b IDRIVEN_HS or IDRIVEN_LS = 1111b IDRIVE = Tied to AGND IDRIVE = 18kΩ ± 5% tied to AGND IDRIVE = 75kΩ ± 5% tied to AGND IDRIVE = Hi-Z IDRIVE = 75kΩ ± 5% tied to DVDD IDRIVE = 18kΩ ± 5% tied to DVDD IDRIVE = Tied to DVDD	880 1140 1360 1640 2000 20 60 120 240 520 1140 2000		mA
I		Source current after t DRIVE	10		mA
HOLD	Gate holding current	Sink current after t DRIVE GHx to SHx	50 480
R OFF	Gate hold off resistor	GLx to PGND	150		kΩ
CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)
G CSA		CSA_GAIN = 00b	5	5.15	V/V
		CSA_GAIN = 01b	10	10.3	V/V
	SPI Device	CSA_GAIN = 10b	20	20.6	V/V
	Amplifier gain	CSA_GAIN = 11b	40	41.2	V/V
		GAIN = Tied to AGND	5	5.15	V/V
		GAIN = 47kΩ ± 5% tied to AGND	10	10.3	V/V
	H/W Device	GAIN = Hi-Z	20	20.6	V/V
		GAIN = Tied to DVDD V O_STEP = 0.5V, G CSA = 5V/V	40 150	41.2	V/V
t (1)	Settling time to ±1%	V O_STEP = 0.5V, G CSA = 10V/V	300		ns
SET		V O_STEP = 0.5V, G CSA = 20V/V V O_STEP = 0.5V, G CSA = 40V/V	600 1200		ns ns
V COM	Common mode input range range			0.15	V V
V DIFF	Differential mode input			0.3

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at T A = -40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)

	PARAMETER	PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
V OFF	Input offset error	Input offset error	V SP = V SN = 0V, CAL = 3.3 , VREF = 3.3V		4	mV
V DRIFT (1)	Drift offset	Drift offset	V SP = V SN = 0V	10		μV/°C
V LINEAR	SOx output voltage linear range	SOx output voltage linear range			V VREF - 0.25	V
V BIAS	SOx output voltage bias	SPI Device	V SP = V SN = 0V, CAL = 3.3V, VREF_DIV = 0b	VREF - 0.3		V
V BIAS	SOx output voltage bias		V SP = V SN = 0V, CAL = 3.3 , VREF_DIV = 1b	V VREF / 2		V
V BIAS	SOx output voltage bias	H/W Device	V SP = V SN = 0V, CAL = 3.3V	V VREF / 2
I BIAS	SPx/SNx input bias current	SPx/SNx input bias current	VREF_DIV = 1b		100	μA
V SLEW (1)	SOx output slew rate	SOx output slew rate	60pF load	10		V/μs
I VREF	VREF input current	VREF input current	V VREF = 5V	2	3	mA
UGB (1)	Unity gain bandwidth	Unity gain bandwidth	60pF load	10		MHz
PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS
V UVLO			VM falling, UVLO report	5.6	5.8	V
V UVLO	VM undervoltage lockout	VM undervoltage lockout	VM rising, UVLO recovery	5.8	6	V
V UVLO_HYS	VM undervoltage hysteresis	VM undervoltage hysteresis	Rising to falling threshold	200		mV
t UVLO_DEG	VM undervoltage deglitch time	VM undervoltage deglitch time	VM falling, UVLO report	10		μs
V CPUV	Charge pump undervoltage lockout	Charge pump undervoltage lockout	VCP falling, CPUV report	V VM + 2.8		V
V GS_CLAMP	High-side gate clamp	High-side gate clamp	Positive clamping voltage Negative clamping voltage	16.5 -0.7	18	V
	V VDS_OCP	SPI Device H/W Device	VDS_LVL = 0000b VDS_LVL = 0001b VDS_LVL = 0010b VDS_LVL = 0011b VDS_LVL = 0100b VDS_LVL = 0101b VDS_LVL = 0110b VDS_LVL = 0111b VDS_LVL = 1000b VDS_LVL = 1001b VDS_LVL = 1010b VDS_LVL = 1011b VDS_LVL = 1100b VDS_LVL = 1101b VDS_LVL = 1110b VDS_LVL = 1111b VDS = Tied to AGND VDS = 18kΩ ± 5% tied to AGND VDS = 75kΩ ± 5% tied to AGND VDS = Hi-Z VDS = 75kΩ ± 5% tied to DVDD VDS = 18kΩ ± 5% tied to DVDD VDS = Tied to DVDD	0.06 0.13 0.2 0.26 0.31 0.45 0.53 0.6 0.68 0.75 0.94 1.13 1.3 1.5 1.7 1.88 0.06 0.13 0.26 0.6 1.13 1.88 Disabled	V

at T A = -40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)

PARAMETER	PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
		SPI Device SPI Device	OCP_DEG = 00b OCP_DEG = 01b		2 4
t OCP_DEG		SPI Device SPI Device H/W Device	OCP_DEG = 10b OCP_DEG = 11b		6 8 4		μs
V SEN_OCP		SPI Device	SEN_LVL = 00b		0.25		V
V SEN_OCP		SPI Device	SEN_LVL = 01b		0.5		V
V SEN_OCP		SPI Device	SEN_LVL = 10b		0.75		V
V SEN_OCP		SPI Device	SEN_LVL = 11b		1		V
V SEN_OCP		H/W Device			1		V
t RETRY		SPI Device	TRETRY = 0b		4		ms
t RETRY		SPI Device	TRETRY = 1b		50		μs
t RETRY		H/W Device			4		ms
T OTW (1)	Thermal warning temperature	Thermal warning temperature	Die temperature, T J	130	150	165	°C
T OTSD (1)	Thermal shutdown temperature	Thermal shutdown temperature	Die temperature, T J	150	170	185	°C
T HYS (1)	Thermal hysteresis	Thermal hysteresis	Die temperature, T J		20		°C
BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)	BUCK REGULATOR SUPPLY (VIN)
I nSHDN			V nSHDN = 0V		1	3	μA
I Q	Shutdown supply current	current	V VIN = 12V, no load; not switching		28		μA
V			VIN Rising			4	V
VIN_UVLO	VIN undervoltage lockout threshold	VIN undervoltage lockout threshold	VIN Falling	3
BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)	BUCK REGULATOR SHUTDOWN (nSHDN)
V nSHDN_TH	Rising nSHDN threshold	Rising nSHDN threshold		1.05	1.25	1.38	V
I nSHDN	Input current	Input current	V nSHDN = 2.3V		-4.2		μA
	Hysteresis current	Hysteresis current	V nSHDN = 0.9V		-1
BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET	BUCK REGULATOR HIGH-SIDE MOSFET
R DS_ON	MOSFET on resistance	MOSFET on resistance	V VIN = 12V, V CB to V SW = 5.8V, T A = 25°C		900		mΩ
BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)	BUCK REGULATOR VOLTAGE REFERENCE (FB)
V FB	Feedback voltage	Feedback voltage		0.747	0.765	0.782	V
BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT
I LIMIT	Peak current limit	Peak current limit	V VIN = 12V, T A = 25°C		1200	1700	mA
BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)	BUCK REGULATOR SWITCHING (SW)
f SW	Switching frequency	Switching frequency		595	700	805	kHz
D MAX	Maximum duty cycle	Maximum duty cycle			96%
BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN
T SHDN (1)	Thermal shutdown threshold	Thermal shutdown threshold			170		°C
T HYS (1)	Thermal shutdown hysteresis	Thermal shutdown hysteresis			10		°C

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DRV8323/PART Absolute Maximum Ratings

at T A = -40°C to +125°C (unless otherwise noted) (1)

	MIN	MAX	UNIT
GATE DRIVER
Power supply pin voltage (VM)	-0.3	65	V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)	-0.3	0.3	V
MOSFET drain sense pin voltage (VDRAIN)	-0.3	65	V
Charge pump pin voltage (CPH, VCP)	-0.3	V VM + 15.5	V
Continuous charge pump negative-switching pin voltage (CPL)	-0.3	V VM + 1	V
Transient 1-us charge pump negative-switching pin voltage (CPL)	-1		V
Internal logic regulator pin voltage (DVDD)	-0.3	3.8	V
Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS)	-0.3	5.75	V
Continuous high-side gate driver output pin voltage (GHx)	-5 (2)	V VCP + 1	V
Transient 200ns high-side gate driver output pin voltage (GHx)	-7	V VCP + 1	V
High-side gate driver output pin voltage with respect to SHx (GHx)	-1.6	18	V
Continuous high-side source pin voltage (SHx)	-5 (2)	V VM + 5	V
Transient 200ns high-side source pin voltage (SHx)	-7	V VM + 7	V
Transient 1-us high-side source pin voltage (SHx)		V VCP - 2	V
Continuous low-side gate driver output pin voltage (GLx)	-0.5	18	V
Transient 200ns low-side gate driver output pin voltage (GLx)	-1.5		V
Gate driver output pin source current (GHx, GLx)	Internally limited	Internally limited	A
Gate driver output pin sink current (GHx, GLx)	Internally limited	Internally limited	A
Continuous voltage at low-side source pin (SLx) and current sense amplifier input pin (SPx, SNx)	-1	1	V
Transient 200ns voltage at low-side source pin (SLx) and current sense amplifier input pin (SPx, SNx)	-3	3	V
Current sense amplifier power supply input and reference pin voltage (VREF)	-0.3	5.75	V
Current sense amplifier output pin voltage (SOx)	-0.3	V VREF + 0.3	V
BUCK REGULATOR
Power supply pin voltage (VIN)	-0.3	65	V
Shutdown control pin voltage (nSHDN)	-0.3	V VIN	V
Voltage feedback pin voltage (FB)	-0.3	7	V
Bootstrap pin voltage with respect to SW (CB)	-0.3	7	V
Switching node pin voltage (SW)	-0.3	V VIN	V
Switching node pin voltage less than 30ns transients (SW)	-2	V VIN	V
DRV832x
Operating junction temperature, T J	-40	150	°C
Storage temperature, T stg	-65	150	°C

(2) Continuous high-side gate driver output pin (GHx) and high-side source pin voltage (SHx) should be limited to -2V minimum for an absolute maximum of 65V on VM or VDRAIN. At 60V and lower, the full specification of -5V continuous on GHx and SHx is allowable.

DRV8323/PART Recommended Operating Conditions

at T A = -40°C to +125°C (unless otherwise noted)

		MIN	MAX	UNIT
GATE DRIVER	GATE DRIVER
V VM	Power supply voltage (VM)	6	60	V
V I	Input voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)	0	5.5	V
f PWM	Applied PWM signal (INHx, INLx)	0	200 (1)	kHz
I GATE_HS	High-side average gate drive current (GHx)	0	25 (1)	mA
I GATE_LS	Low-side average gate drive current (GLx)	0	25 (1)	mA
I DVDD	External load current (DVDD)	0	30 (1)	mA
V VREF	Current sense amplifier power supply input and reference (VREF)	3	5.5	V
I SO	Current sense amplifier output current (SOx)	0	5	mA
V OD	Open drain pin pullup voltage (nFAULT, SDO)	0	5.5	V
I OD	Open drain pin output current (nFAULT, SDO)	0	5	mA
BUCK REGULATOR	BUCK REGULATOR
V VIN	Power supply voltage (VIN)	4	60	V
V nSHDN	Shutdown control input voltage (nSHDN)	0	60	V
DRV832x	DRV832x
T A	Operating ambient temperature	-40	125	°C

DRV8323/PART Thermal Information

		DRV832x	DRV832x	DRV832x	DRV832x
THERMAL METRIC (1)	THERMAL METRIC (1)	RTV (WQFN)	RHA (VQFN)	RTA (WQFN)	RGZ (VQFN)	UNIT
		32 PINS	40 PINS	40 PINS	48 PINS
R θJA	Junction-to-ambient thermal resistance	32.9	30.1	32.1	26.6	°C/W
R θJC(top)	Junction-to-case (top) thermal resistance	15.8	16.7	11	13.9	°C/W
R θJB	Junction-to-board thermal resistance	6.8	9.9	7.1	9.2	°C/W
ψ JT	Junction-to-top characterization parameter	0.2	0.5	0.1	0.3	°C/W
ψ JB	Junction-to-board characterization parameter	6.8	9.9	7.1	9.1	°C/W
R θJC(bot)	Junction-to-case (bottom) thermal resistance	2.1	2.2	2.1	2	°C/W

DRV8323/PART Typical Application

The DRV832x family of devices is primarily used in applications for three-phase brushless DC motor control. The design procedures in Section 9.2 highlight how to use and configure the DRV832x family of devices.

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