CY8C4146AZI-S445
The CY8C4146AZI-S445 is an electronic component from now Infineon. View the full CY8C4146AZI-S445 datasheet below including absolute maximum ratings.
Manufacturer
now Infineon
Overview
Part: PSoC 4100S Plus — Infineon Technologies (Cypress)
Type: Programmable System-on-Chip (PSoC) / Microcontroller (MCU)
Description: A scalable and reconfigurable platform architecture for programmable embedded system controllers with an Arm Cortex-M0+ CPU, featuring up to 128 KB Flash, 16 KB SRAM, CapSense, programmable analog and digital blocks, and flexible routing.
Operating Conditions:
- Supply voltage: 1.71–5.5 V
- CPU clock frequency: 48 MHz
Absolute Maximum Ratings:
Key Specs:
- CPU: 48-MHz Arm Cortex-M0+
- Flash memory: Up to 128 KB
- SRAM memory: Up to 16 KB
- DMA engine: 8-channel
- SAR ADC: 12-bit, 1-Msps
- Opamps: Two, reconfigurable
- Serial Communication Blocks (SCBs): Five, reconfigurable I2C, SPI, or UART
Features:
- Capacitive touch-sensing system (CapSense) with best-in-class SNR and water tolerance
- Programmable general-purpose continuous-time and switched-capacitor analog blocks
- Programmable logic blocks for Boolean operations
- Low-power operation with Deep Sleep mode (2.5-μA digital system current)
- LCD segment drive capability on GPIOs
- Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- True Random Number Generator (TRNG)
- CAN 2.0B block with support for Time-Triggered CAN (TTCAN)
- Up to 54 programmable GPIO pins
- ModusToolbox™ Software and PSoC Creator design environment
Applications:
Package:
- 44-pin TQFP (0.8-mm pitch)
- 48-pin TQFP (0.5-mm pitch)
- 64-pin TQFP (0.8 mm)
- 64-pin TQFP Fine Pitch (0.5 mm)
Pin Configuration
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table.
| Port/Pin | Analog | Smart I/O | ACT #0 | ACT #1 | ACT #3 | DS #2 | DS #3 |
|---|---|---|---|---|---|---|---|
| P0.0 | lpcomp.in_p[0] | tcpwm.tr_in[0] | scb[2].uart_cts:0 | scb[2].i2c_scl:0 | scb[0].spi_select1:0 | ||
| P0.1 | lpcomp.in_n[0] | tcpwm.tr_in[1] | scb[2].uart_rts:0 | scb[2].i2c_sda:0 | scb[0].spi_select2:0 | ||
| P0.2 | lpcomp.in_p[1] | scb[0].spi_select3:0 | |||||
| P0.3 | lpcomp.in_n[1] | scb[2].spi_select0:1 | |||||
| P0.4 | wco.wco_in | scb[1].uart_rx:0 | scb[2].uart_rx:0 | scb[1].i2c_scl:0 | scb[1].spi_mosi:1 | ||
| P0.5 | wco.wco_out | scb[1].uart_tx:0 | scb[2].uart_tx:0 | scb[1].i2c_sda:0 | scb[1].spi_miso:1 | ||
| P0.6 | exco.eco_in | srss.ext_clk:0 | scb[1].uart_cts:0 | scb[2].uart_tx:1 | scb[1].spi_clk:1 | ||
| P0.7 | exco.eco_out | tcpwm.line[0]:3 | scb[1].uart_rts:0 | scb[1].spi_select0:1 | |||
| P5.0 | tcpwm.line[4]:2 | scb[2].uart_rx:1 | scb[2].i2c_scl:1 | scb[2].spi_mosi:0 | |||
| P5.1 | tcpwm.line_compl[4]:2 | scb[2].uart_tx:2 | scb[2].i2c_sda:1 | scb[2].spi_miso:0 | |||
| P5.2 | tcpwm.line[5]:2 | scb[2].uart_cts:1 | lpcomp.comp[0]:2 | scb[2].spi_clk:0 | |||
| P5.3 | tcpwm.line_compl[5]:2 | scb[2].uart_rts:1 | lpcomp.comp[1]:0 | scb[2].spi_select0:0 | |||
| P5.4 | tcpwm.line[6]:2 | scb[2].spi_select1:0 | |||||
| P5.5 | tcpwm.line_compl[6]:2 | scb[2].spi_select2:0 | |||||
| P1.0 | ctb0_oa0+ | SmartIo[2].io[0] | tcpwm.line[2]:1 | scb[0].uart_rx:1 | scb[0].i2c_scl:0 | scb[0].spi_mosi:1 | |
| P1.1 | ctb0_oa0- | SmartIo[2].io[1] | tcpwm.line_compl[2]:1 | scb[0].uart_tx:1 | scb[0].i2c_sda:0 | scb[0].spi_miso:1 | |
| P1.2 | ctb0_oa0_out | SmartIo[2].io[2] | tcpwm.line[3]:1 | scb[0].uart_cts:1 | tcpwm.tr_in[2] | scb[2].i2c_scl:2 | scb[0].spi_clk:1 |
| P1.3 | ctb0_oa1_out | SmartIo[2].io[3] | tcpwm.line_compl[3]:1 | scb[0].uart_rts:1 | tcpwm.tr_in[3] | scb[2].i2c_sda:2 | scb[0].spi_select0:1 |
| P1.4 | ctb0_oa1- | SmartIo[2].io[4] | tcpwm.line[6]:1 | scb[3].i2c_scl:0 | scb[0].spi_select1:1 | ||
| P1.5 | ctb0_oa1+ | SmartIo[2].io[5] | tcpwm.line_compl[6]:1 | scb[3].i2c_sda:0 | scb[0].spi_select2:1 | ||
| P1.6 | ctb0_oa0+ | SmartIo[2].io[6] | tcpwm.line[7]:1 | scb[0].spi_select3:1 | |||
| P1.7 | ctb0_oa1+ sar_ext_vref0 sar_ext_vref1 | SmartIo[2].io[7] | tcpwm.line_compl[7]:1 | scb[2].spi_clk:1 | |||
| P2.0 | sarmux[0] | SmartIo[0].io[0] | tcpwm.line[4]:0 | csd.comp | tcpwm.tr_in[4] | scb[1].i2c_scl:1 | scb[1].spi_mosi:2 |
| P2.1 | sarmux[1] | SmartIo[0].io[1] | tcpwm.line_compl[4]:0 | tcpwm.tr_in[5] | scb[1].i2c_sda:1 | scb[1].spi_miso:2 | |
| P2.2 | sarmux[2] | SmartIo[0].io[2] | tcpwm.line[5]:1 | scb[1].spi_clk:2 | |||
| P2.3 | sarmux[3] | SmartIo[0].io[3] | tcpwm.line_compl[5]:1 | scb[1].spi_select0:2 |
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings [1]
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID1 | V DDD_ABS | Digital supply relative to V SS | -0.5 | - | 6 | V | - |
| SID2 | V CCD_ABS | Direct digital core voltage input relative to V SS | -0.5 | - | 1.95 | V | - |
| SID3 | V GPIO_ABS | GPIO voltage | -0.5 | - | V DD +0.5 | V | - |
| SID4 | I GPIO_ABS | Maximum current per GPIO | -25 | - | 25 | mA | - |
| SID5 | I GPIO_injection | GPIO injection current, Max for V IH > V DDD , and Min for V IL < V SS | -0.5 | - | 0.5 | mA | Current injected per pin |
| BID44 | ESD_HBM | Electrostatic discharge human body model | 2200 | - | - | V | - |
| BID45 | ESD_CDM | Electrostatic discharge charged device model | 500 | - | - | V | - |
| BID46 | LU | Pin current for latch-up | -140 | - | 140 | mA | - |
Thermal Information
| Parameter | Description | Package | Min | Typ | Max | Units |
|---|---|---|---|---|---|---|
| T A | Operating ambient temperature | - | -40 | 25 | 105 | °C |
| T J | Operating junction temperature | - | -40 | - | 125 | °C |
| T JA | Package θ JA | 44-pin TQFP | - | 55.6 | - | °C/Watt |
| T JC | Package θ JC | 44-pin TQFP | - | 14.4 | - | °C/Watt |
| T JA | Package θ JA | 64-pin TQFP (0.5-mm pitch) | - | 46 | - | °C/Watt |
| T JC | Package θ JC | 64-pin TQFP (0.5-mm pitch) | - | 10 | - | °C/Watt |
| T JA | Package θ JA | 64-pin TQFP (0.8-mm pitch) | - | 36.8 | - | °C/Watt |
| T JC | Package θ JC | 64-pin TQFP (0.8-mm pitch) | - | 9.4 | - | °C/Watt |
| T JA | Package θ JA | 48-pin TQFP (0.5-mm pitch) | - | 39.4 | - | °C/Watt |
| T JC | Package θ JC | 48-pin TQFP (0.5-mm pitch) | - | 9.3 | - | °C/Watt |
Table 42. Solder Reflow Peak Temperature
| Package | Maximum Peak Temperature | Maximum Time at Peak Temperature |
|---|---|---|
| All | 260 °C | 30 seconds |
Table 43. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
| Package | MSL |
|---|---|
| All | MSL 3 |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| CY8C4146AXI | now Infineon | TQFP-44 |
| CY8C4146AXI-S443 | now Infineon | — |
| CY8C4146AXI-S445 | now Infineon | — |
| CY8C4146AXI-S453 | now Infineon | — |
| CY8C4146AXI-S455 | now Infineon | — |
| CY8C4146AZI-S443 | now Infineon | — |
| CY8C4146AZI-S453 | now Infineon | TQFP |
| CY8C4146AZI-S455 | now Infineon | — |
| CY8C4146AZI-S463 | now Infineon | — |
| CY8C4146AZQ-S445 | now Infineon | — |
| CY8C4146AZQ-S455 | now Infineon | — |
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