CY8C4146AZI-S443
Please note that Cypress is an Infineon Technologies Company.
Manufacturer
now Infineon
Overview
Part: PSoC 4100S Plus from Cypress (now Infineon)
Type: Programmable System-on-Chip (PSoC) with Arm Cortex-M0+ CPU
Key Specs:
- CPU: 48-MHz Arm Cortex-M0+
- Flash: Up to 128 KB
- SRAM: Up to 16 KB
- SAR ADC: 12-bit 1-Msps
- Operating Voltage: 1.71-V to 5.5-V
- Deep Sleep Digital System Current: 2.5-μA
- CapSense SNR: >5:1
- External Crystal Oscillator: 4 to 33 MHz
- PLL Frequency: 48-MHz
- Watch Crystal Oscillator: 32-kHz
- Internal Main Oscillator Accuracy: ±2%
- Internal Low-power Oscillator: 32-kHz
- Programmable GPIO Pins: Up to 54
Features:
- 32-bit MCU Subsystem with 48-MHz Arm Cortex-M0+ CPU, up to 128 KB flash, up to
Features
32-bit MCU Subsystem
- 48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
- Up to 128 KB of flash with Read Accelerator
- Up to 16 KB of SRAM
- 8-channel DMA engine
Programmable Analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averaging
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
Programmable Digital
■ Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■ Deep Sleep mode with operational analog and 2.5-μA digital system current
Capacitive Sensing
- Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Cypress-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■ LCD segment drive capability on GPIOs
Serial Communication
■ Five independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality
Timing and Pulse-Width Modulation
- Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
Clock Sources
- 4 to 33 MHz external crystal oscillator (ECO)
- PLL to generate 48-MHz frequency
- 32-kHz Watch Crystal Oscillator (WCO)
- ±2% Internal Main Oscillator (IMO)
- 32-kHz Internal Low-power Oscillator (ILO)
True Random Number Generator (TRNG)
■ TRNG generates truly random number for secure key generation for Cryptography applications
CAN Block
■ CAN 2.0B block with support for Time-Triggered CAN (TTCAN)
Up to 54 Programmable GPIO Pins
- 44-pin TQFP (0.8-mm pitch), 48-pin TQFP (0.5-mm pitch), and 64-pin TQFP normal (0.8 mm) and Fine Pitch (0.5 mm) packages
- Any GPIO pin can be CapSense, analog, or digital
- Drive modes, strengths, and slew rates are programmable
ModusToolbox™ Software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CapSense
PSoC Creator Design Environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital automatic routing
- Application programming interface (API) Components for all fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■ After schematic entry, development can be done with Arm-based industry-standard development tools
Pin Configuration
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table.
| Po / P in t r | An log a | Sm I / O t ar | A C T # 0 | A C T # 1 | A C T # 3 | D S # 2 | D S # 3 |
|---|---|---|---|---|---|---|---|
| P 0. 0 | lp in_ [ 0 ] co mp p | tcp tr_ in [ 0 ] wm | b [ 2 ]. t_ ts: 0 sc ua r c | b [ 2 ]. i 2c l: 0 sc sc _ | b [ 0 ]. i_ lec t 1: 0 sc sp se | ||
| P 0. 1 | lp in_ [ 0 ] co mp n | tcp tr_ in [ 1 ] wm | b [ 2 ]. t_ ts: 0 sc ua r r | b [ 2 ]. i 2c da 0 sc s : _ | b [ 0 ]. i_ lec t 2: 0 sc sp se | ||
| P 0. 2 | lp in_ [ 1 ] co mp p | b [ 0 ]. i_ lec 3: 0 t sc sp se | |||||
| P 0. 3 | lp in_ [ 1 ] co mp n | b [ 2 ]. i_ lec 0: 1 t sc sp se | |||||
| P 0. 4 | in wc o.w co _ | b [ 1 ]. t_ 0 sc ua r rx: | b [ 2 ]. t_ 0 sc ua r rx: | b [ 1 ]. i 2c l: 0 sc sc _ | b [ 1 ]. i_ i: 1 sc sp mo s | ||
| P 0. 5 | t wc o.w co ou _ | b [ 1 ]. t_ tx: 0 sc ua r | b [ 2 ]. t_ tx: 0 sc ua r | b [ 1 ]. i 2c da 0 sc s : _ | b [ 1 ]. i_ iso 1 sc sp m : | ||
| P 0. 6 | in ex co .ec o_ | l k: 0 t_ srs s.e x c | b [ 1 ]. 0 t_ ts: sc ua r c | b [ 2 ]. 1 t_ tx: sc ua r | b [ 1 ]. i_ l k: 1 sc sp c | ||
| P 0. 7 | t ex co .ec o_ ou | l ine [ 0 ] 3 tcp wm : | b [ 1 ]. 0 t_ ts: sc ua r r | b [ 1 ]. i_ lec 0: 1 t sc sp se | |||
| P 5. 0 | tcp l ine [ 4 ] 2 wm : | b [ 2 ]. t_ 1 sc ua r rx: | b [ 2 ]. i 2c l: 1 sc sc _ | b [ 2 ]. i_ i: 0 sc sp mo s | |||
| P 5. 1 | tcp l ine l [ 4 ] 2 wm co mp : _ | b [ 2 ]. t_ tx: 2 sc ua r | b [ 2 ]. i 2c da 1 sc s : _ | b [ 2 ]. i_ iso 0 sc sp m : | |||
| P 2 5. | l ine [ ] 2 tcp 5 wm : | b [ 2 ]. 1 t_ ts: sc ua r c | lp [ 0 ] 2 co mp .co mp : | b [ 2 ]. i_ l k: 0 sc sp c | |||
| P 5. 3 | tcp l ine l [ 5 ] 2 wm co mp : _ | b [ 2 ]. t_ ts: 1 sc ua r r | lp [ 1 ] 0 co mp .co mp : | b [ 2 ]. i_ lec t 0: 0 sc sp se | |||
| P 5. 4 | tcp l ine [ 6 ] 2 wm : | b [ 2 ]. i_ lec t 1: 0 sc sp se | |||||
| P 5. 5 | tcp l ine l [ 6 ] 2 wm co mp : _ | b [ 2 ]. i_ lec t 2: 0 sc sp se | |||||
| P 1. 0 | b 0_ 0+ t c oa | Sm Io [ 2 ]. io [ 0 ] t ar | l ine [ 2 ] 1 tcp wm : | b [ 0 ]. 1 t_ sc ua r rx: | b [ 0 ]. i 2c l: 0 sc sc _ | b [ 0 ]. i_ i: 1 sc sp mo s | |
| P 1. 1 | b 0_ 0- t c oa | Sm Io [ 2 ]. io [ 1 ] t ar | l ine l [ 2 ] 1 tcp wm co mp : _ | b [ 0 ]. 1 t_ tx: sc ua r | b [ 0 ]. i 2c da 0 sc s : _ | b [ 0 ]. i_ iso 1 sc sp m : | |
| P 1. 2 | t b 0_ 0_ t c oa ou | Sm t Io [ 2 ]. io [ 2 ] ar | tcp l ine [ 3 ] 1 wm : | b [ 0 ]. t_ ts: 1 sc ua r c | tcp tr_ in [ 2 ] wm | b [ 2 ]. i 2c l: 2 sc sc _ | b [ 0 ]. i_ l k: 1 sc sp c |
| P 1. 3 | t b 0_ 1_ t c oa ou | Sm t Io [ 2 ]. io [ 3 ] ar | tcp l ine l [ 3 ] 1 wm co mp : _ | b [ 0 ]. t_ ts: 1 sc ua r r | tcp tr_ in [ 3 ] wm | b [ 2 ]. i 2c da 2 sc s : _ | b [ 0 ]. i_ lec t 0: 1 sc sp se |
| P 1. 4 | t b 0_ 1- c oa | Sm t Io [ 2 ]. io [ 4 ] ar | tcp l ine [ 6 ] 1 wm : | b [ 3 ]. i 2c l: 0 sc sc _ | b [ 0 ]. i_ lec t 1: 1 sc sp se | ||
| P 1. 5 | t b 0_ 1+ c oa | Sm t Io [ 2 ]. io [ 5 ] ar | tcp l ine l [ 6 ] 1 wm co mp : _ | b [ 3 ]. i 2c da 0 sc s : _ | b [ 0 ]. i_ lec t 2: 1 sc sp se | ||
| P 1. 6 | b 0_ 0+ t c oa | Sm Io [ 2 ]. io [ 6 ] t ar | l ine [ ] 1 tcp 7 wm : | b [ 0 ]. i_ lec 3: 1 t sc sp se | |||
| P 1. 7 | t b 0_ 1+ c oa f 0 t_ sa r_ ex vre t_ f 1 sa r_ ex vre | Sm t Io [ 2 ]. io [ 7 ] ar | tcp l ine l [ 7 ] 1 wm co mp : _ | b [ 2 ]. i_ l k: 1 sc sp c | |||
| P 2. 0 | [ 0 ] sa rm ux | Sm Io [ 0 ]. io [ 0 ] t ar | l ine [ 4 ] 0 tcp wm : | d.c cs om p | in [ 4 ] tcp tr_ wm | b [ 1 ]. i 2c l: 1 sc sc _ | b [ 1 ]. i_ i: 2 sc sp mo s |
| P 2. 1 | [ 1 ] sa rm ux | Sm t Io [ 0 ]. io [ 1 ] ar | tcp l ine l [ 4 ] 0 wm co mp : _ | tcp tr_ in [ 5 ] wm | b [ 1 ]. i 2c da 1 sc s : _ | b [ 1 ]. i_ iso 2 sc sp m : | |
| P 2. 2 | [ 2 ] sa rm ux | Sm t Io [ 0 ]. io [ 2 ] ar | tcp l ine [ 5 ] 1 wm : | b [ 1 ]. i_ l k: 2 sc sp c | |||
| P 2. 3 | [ 3 ] sa rm ux | Sm Io [ 0 ]. io [ 3 ] t ar | l ine l [ ] 1 tcp 5 wm co mp : _ | b [ 1 ]. i_ lec 0: 2 t sc sp se |
| Po t / P in r | An log a | Sm t I / O ar | A C T # 0 | A C T # 1 | A C T # 3 | D S # 2 | D S # 3 |
|---|---|---|---|---|---|---|---|
| P 2. 4 | [ 4 ] sa rm ux | Sm t Io [ 0 ]. io [ 4 ] ar | tcp l ine [ 0 ] 1 wm : | b [ 3 ]. t_ 1 sc ua r rx: | b [ 1 ]. i_ lec t 1: 1 sc sp se | ||
| 2. P 5 | [ 5 ] sa rm ux | Sm 0 t Io [ ]. io [ 5 ] ar | 0 1 tcp l ine l [ ] wm co mp : _ | 3 1 b [ ]. t_ tx: sc ua r | 1 2: 1 b [ ]. i_ lec t sc sp se | ||
| P 2. 6 | [ 6 ] sa rm ux | Sm Io [ 0 ]. io [ 6 ] t ar | l ine [ 1 ] 1 tcp wm : | b [ 3 ]. 1 t_ ts: sc ua r c | b [ 1 ]. i_ lec 3: 1 t sc sp se | ||
| P 2. 7 | [ ] 7 sa rm ux | Sm Io [ 0 ]. io [ ] t 7 ar | l ine l [ 1 ] 1 tcp wm co mp : _ | b [ 3 ]. 1 t_ ts: sc ua r r | lp [ 0 ] 0 co mp .co mp : | b [ 2 ]. i_ i: 1 sc sp mo s | |
| 6. 0 P | 1 tcp l ine [ 4 ] wm : | 3 0 b [ ]. t_ sc ua r rx: | 0 tx_ b_ ca n.c an en n: _ | 3 2c 1 b [ ]. i l: sc sc _ | 3 0 b [ ]. i_ i: sc sp mo s | ||
| P 6. 1 | l ine l [ 4 ] 1 tcp wm co mp : _ | b [ 3 ]. 0 t_ tx: sc ua r | 0 ca n.c an rx: _ | b [ 3 ]. i 2c da 1 sc s : _ | b [ 3 ]. i_ iso 0 sc sp m : | ||
| P 6. 2 | tcp l ine [ 5 ] 0 wm : | b [ 3 ]. t_ ts: 0 sc ua r c | tx: 0 ca n.c an _ | b [ 3 ]. i_ l k: 0 sc sp c | |||
| P 6. 3 | tcp l ine l [ 5 ] 0 wm co mp : _ | b [ 3 ]. t_ ts: 0 sc ua r r | b [ 3 ]. i_ lec t 0: 0 sc sp se | ||||
| P 6. 4 | l ine [ 6 ] 0 tcp wm : | b [ 4 ]. i 2c l sc sc _ | b [ 3 ]. i_ lec 1: 0 t sc sp se | ||||
| P 6. 5 | tcp l ine l [ 6 ] 0 wm co mp : _ | b [ 4 ]. i 2c da sc s _ | b [ 3 ]. i_ lec t 2: 0 sc sp se | ||||
| P 3. 0 | Sm t Io [ 1 ]. io [ 0 ] ar | tcp l ine [ 0 ] 0 wm : | b [ 1 ]. t_ 1 sc ua r rx: | b [ 1 ]. i 2c l: 2 sc sc _ | b [ 1 ]. i_ i: 0 sc sp mo s | ||
| P 3. 1 | Sm t Io [ 1 ]. io [ 1 ] ar | tcp l ine l [ 0 ] 0 wm co mp : _ | b [ 1 ]. t_ tx: 1 sc ua r | b [ 1 ]. i 2c da 2 sc s : _ | b [ 1 ]. i_ iso 0 sc sp m : | ||
| P 3. 2 | Sm Io [ 1 ]. io [ 2 ] t ar | l ine [ 1 ] 0 tcp wm : | b [ 1 ]. 1 t_ ts: sc ua r c | d_ da ta cp us s.s w | b [ 1 ]. i_ l k: 0 sc sp c | ||
| P 3. 3 | Sm t Io [ 1 ]. io [ 3 ] ar | tcp l ine l [ 1 ] 0 wm co mp : _ | b [ 1 ]. t_ ts: 1 sc ua r r | d_ l k cp us s.s w c | b [ 1 ]. i_ lec t 0: 0 sc sp se | ||
| P 3. 4 | Sm t Io [ 1 ]. io [ 4 ] ar | tcp l ine [ 2 ] 0 wm : | tcp tr_ in [ 6 ] wm | b [ 1 ]. i_ lec t 1: 0 sc sp se | |||
| 3. P 5 | Sm 1 t Io [ ]. io [ 5 ] ar | 2 0 tcp l ine l [ ] wm co mp : _ | 1 2: 0 b [ ]. i_ lec t sc sp se | ||||
| P 3. 6 | Sm Io [ 1 ]. io [ 6 ] t ar | l ine [ 3 ] 0 tcp wm : | b [ 4 ]. i_ lec 3 t sc sp se | b [ 1 ]. i_ lec 3: 0 t sc sp se | |||
| P 3. 7 | Sm t Io [ 1 ]. io [ 7 ] ar | tcp l ine l [ 3 ] 0 wm co mp : _ | lp [ 1 ] 1 co mp .co mp : | b [ 2 ]. i_ iso 1 sc sp m : | |||
| P 4. 0 | d.v f_ t cs re ex | b [ 0 ]. t_ 0 sc ua r rx: | 1 ca n.c an rx: _ | b [ 0 ]. i 2c l: 1 sc sc _ | b [ 0 ]. i_ i: 0 sc sp mo s | ||
| 1 P 4. | d.c h ie l d cs s | 0 0 b [ ]. t_ tx: sc ua r | 1 tx: ca n.c an _ | 0 2c 1 b [ ]. i da sc s : _ | 0 0 b [ ]. i_ iso sc sp m : | ||
| P 4. 2 | d.c d cs mo | b [ 0 ]. 0 t_ ts: sc ua r c | b_ 1 tx_ ca n.c an en n: _ | lp [ 0 ] 1 co mp .co mp : | b [ 0 ]. i_ l k: 0 sc sp c | ||
| P 4. 3 | d.c h_ tan k cs s | b [ 0 ]. t_ ts: 0 sc ua r r | lp [ 1 ] 2 co mp .co mp : | b [ 0 ]. i_ lec t 0: 0 sc sp se | |||
| P 4. 4 | b [ 4 ]. t_ sc ua r rx | b [ 4 ]. i_ i sc sp mo s | b [ 0 ]. i_ lec t 1: 2 sc sp se | ||||
| P 4. 5 | b [ 4 ]. t_ tx sc ua r | b [ 4 ]. i_ iso sc sp m | b [ 0 ]. i_ lec 2: 2 t sc sp se | ||||
| P 4. 6 | b [ 4 ]. t_ ts sc ua r c | b [ 4 ]. i_ l k sc sp c | b [ 0 ]. i_ lec t 3: 2 sc sp se | ||||
| P 4. 7 | b [ 4 ]. t_ ts sc ua r r | b [ 4 ]. i_ lec t 0 sc sp se | |||||
| P 5. 6 | tcp l ine [ 7 ] 0 wm : | b [ 4 ]. i_ lec t 1 sc sp se | b [ 2 ]. i_ lec t 3: 0 sc sp se | ||||
| P 5. 7 | l ine l [ ] 0 tcp 7 wm co mp : _ | b [ 4 ]. i_ lec 2 t sc sp se | |||||
| P 7. 0 | tcp l ine [ 0 ] 2 wm : | b [ 3 ]. t_ 2 sc ua r rx: | b [ 3 ]. i 2c l: 2 sc sc _ | b [ 3 ]. i_ i: 1 sc sp mo s | |||
| P 7. 1 | tcp l ine l [ 0 ] 2 wm co mp : _ | b [ 3 ]. t_ tx: 2 sc ua r | b [ 3 ]. i 2c da 2 sc s : _ | b [ 3 ]. i_ iso 1 sc sp m : | |||
| 2 P 7. | 1 2 tcp l ine [ ] wm : | 3 2 b [ ]. t_ ts: sc ua r c | 3 1 b [ ]. i_ l k: sc sp c |
Electrical Characteristics
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID1 | VDDD_ABS | Digital supply relative to VSS | –0.5 | – | 6 | – | |
| SID2 | VCCD_ABS | Direct digital core voltage input relative to VSS | –0.5 | – | 1.95 | V | – |
| SID3 | VGPIO_ABS | GPIO voltage | –0.5 | – | VDD+0.5 | – | |
| SID4 | IGPIO_ABS | Maximum current per GPIO | –25 | – | 25 | mA | – |
| SID5 | IGPIO_injection | GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS | –0.5 | – | 0.5 | mA | Current injected per pin |
| BID44 | ESD_HBM | Electrostatic discharge human body model | 2200 | – | – | V | – |
| BID45 | ESD_CDM | Electrostatic discharge charged device model | 500 | – | – | V | – |
| BID46 | LU | Pin current for latch-up | –140 | – | 140 | mA | – |
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID53 | VDD | Power supply input voltage | 1.8 | – | 5.5 | Internally regulated supply | |
| SID255 | VDD | Power supply input voltage (VCCD = VDDD = VDDA) | 1.71 | – | 1.89 | V | Internally unregulated supply |
| SID54 | VCCD | Output voltage (for core logic) | – | 1.8 | – | – | |
| SID55 | CEFC | External regulator voltage (VCCD) bypass | – | 0.1 | – | X5R ceramic or better | |
| SID56 | CEXC | Power supply bypass capacitor | – | 1 | – | μF | X5R ceramic or better |
| Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C. | |||||||
| SID10 | IDD5 | Execute from flash; CPU at 6 MHz | – | 1.8 | 2.4 | mA | |
| SID16 | IDD8 | Execute from flash; CPU at 24 MHz | – | 3.0 | 4.6 | mA | |
| SID19 | IDD11 | Execute from flash; CPU at 48 MHz | – | 5.4 | 7.1 | mA | |
| Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) | |||||||
| SID22 | IDD17 | I²C wakeup WDT, and Comparators on | – | 1.1 | 1.8 | mA | 6 MHZ |
| SID25 | IDD20 | I²C wakeup, WDT, and Comparators on | – | 1.5 | 2.1 | mA | 12 MHZ |
| Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) |
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID1 | VDD_ABS | Digital supply relative to VSS | –0.5 | – | 6 | V | – |
| SID2 | VCCD_ABS | Direct digital core voltage input relative to VSS | –0.5 | – | 1.95 | V | – |
| SID3 | VGPIO_ABS | GPIO voltage | –0.5 | – | VDD+0.5 | V | – |
| SID4 | IGPIO_ABS | Maximum current per GPIO | –25 | – | 25 | mA | – |
Table 3. AC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID48 | FCPU | CPU frequency | DC | – | 48 | MHz | 1.71 ≤ VDD ≤ 5.5 |
| SID49[2] | TSLEEP | Wakeup from Sleep mode | – | 0 | – | μs | |
| SID50[2] | TDEEPSLEEP | Wakeup from Deep Sleep mode | – | 35 | – | μs |
GPIO
Table 4. GPIO DC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID57 | VIH[3] | Input voltage high threshold | 0.7 VDDD | – | – | CMOS Input | |
| SID58 | VIL | Input voltage low threshold | – | – | 0.3 VDDD | CMOS Input | |
| SID241 | VIH[3] | LVTTL input, VDDD < 2.7 V | 0.7 VDDD | – | – | – | |
| SID242 | VIL | LVTTL input, VDDD < 2.7 V | – | – | 0.3 VDDD | – | |
| SID243 | VIH[3] | 2.7 V LVTTL input, VDDD | 2.0 | – | – | – | |
| SID244 | VIL | 2.7 V LVTTL input, VDDD | – | – | 0.8 | V | – |
| SID59 | VOH | Output voltage high level | VDDD –0.6 | – | – | IOH = 4 mA at 3 V VDDD | |
| SID60 | VOH | Output voltage high level | VDDD –0.5 | – | – | IOH = 1 mA at 1.8 V VDDD | |
| SID61 | VOL | Output voltage low level | – | – | 0.6 | IOL = 4 mA at 1.8 V VDDD | |
| SID62 | VOL | Output voltage low level | – | – | 0.6 | IOL = 10 mA at 3 V VDDD | |
| SID62A | VOL | Output voltage low level | – | – | 0.4 | IOL = 3 mA at 3 V VDDD | |
| SID63 | RPULLUP | Pull-up resistor | 3.5 | 5.6 | 8.5 | kΩ | – |
| SID64 | RPULLDOWN | Pull-down resistor | 3.5 | 5.6 | 8.5 | – | |
| SID65 | IIL | Input leakage current (absolute value) | – | – | 2 | nA | 25 °C, VDDD = 3.0 V |
| SID66 | CIN | Input capacitance | – | – | 7 | pF | – |
| SID67[4] | VHYSTTL | Input hysteresis LVTTL | 25 | 40 | – | VDDD 2.7 V | |
| SID68[4] | VHYSCMOS | Input hysteresis CMOS | 0.05 × VDDD | – | – | mV | VDD < 4.5 V |
| SID68A[4] | VHYSCMOS5V5 | Input hysteresis CMOS | 200 | – | – | VDD > 4.5 V | |
| SID69[4] | IDIODE | Current through protection diode to VDD/VSS | – | – | 100 | μA | – |
| SID69A[4] | ITOT_GPIO | Maximum total source or sink chip current | – | – | 200 | mA | – |
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID28 | IDD23 | I²C wakeup, WDT, and Comparators on | – | 1.1 | 1.8 | mA | 6 MHZ |
| SID28A | IDD23A | I²C wakeup, WDT, and Comparators on | – | 1.5 | 2.1 | mA | 12 MHZ |
| SID30 | IDD25 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 40 | µA | T = –40 °C to 60 °C |
| SID31 | IDD26 | I²C wakeup and WDT on | – | 2.5 | 125 | µA | Max is at 3.6 V and 85 °C |
| SID33 | IDD28 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 40 | µA | T = –40 °C to 60 °C |
| SID34 | IDD29 | I²C wakeup and WDT on | – | 2.5 | 125 | µA | Max is at 5.5 V and 85 °C |
| SID36 | IDD31 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 60 | µA | T = –40 °C to 60 °C |
| SID37 | IDD32 | I²C wakeup and WDT on | – | 2.5 | 180 | µA | Max is at 1.89 V and 85 °C |
| SID307 | IDD_XR | Supply current while XRES asserted | – | 2 | 5 | mA | – |
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID48 | FCPU | CPU frequency | DC | – | 48 | MHz | 1.71 ≤ VDD ≤ 5.5 |
| SID49[2] | TSLEEP | Wakeup from Sleep mode | – | 0 | – | µs | – |
| SID50[2] | TDEEPSLEEP | Wakeup from Deep Sleep mode | – | 35 | – | µs | – |
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Table 5. GPIO AC Specifications (continued)
(Guaranteed by Characterization)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID70 | TRISEF | Rise time in fast strong mode | 2 | – | 12 | ns | 3.3 V VDDD, Cload = 25 pF |
| SID71 | TFALLF | Fall time in fast strong mode | 2 | – | 12 | ns | 3.3 V VDDD, Cload = 25 pF |
| SID72 | TRISES | Rise time in slow strong mode | 10 | – | 60 | ns | 3.3 V VDDD, Cload |
XRES
Table 6. XRES DC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID57 | V_IH[3] | Input voltage high threshold | 0.7 × V_DDD | – | – | V | CMOS Input |
| SID58 | V_IL | Input voltage low threshold | – | – | 0.3 × V_DDD | V | CMOS Input |
| SID241 | V_IH[3] | LVTTL input, V_DDD < 2.7 V | 0.7 × V_DDD | – | – | V | – |
| SID242 | V_IL | LVTTL input, V_DDD < 2.7 V | – | – | 0.3 × V_DDD | V | – |
| SID243 | V_IH[3] | LVTTL input, V_DDD ≥ 2.7 V | 2.0 | – | – | V | – |
| SID244 | V_IL | LVTTL input, V_DDD ≥ 2.7 V | – | – | 0.8 | V | – |
| SID59 | V_OH | Output voltage high level | V_DDD – 0.6 | – | – | V | I_OH = |
Table 7. XRES AC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID83[5] | TRESETWIDTH | Reset pulse width | 1 | – | – | μs | – |
| BID194[5] | TRESETWAKE | Wake-up time from reset release | – | – | 2.7 | ms | – |
Analog Peripherals
CTBm Opamp
Table 8. CTBm Opamp Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | ||||||
| SID269 | IDD_HI | power = hi | – | 1100 | 1850 | μA | – |
| SID270 | IDD_MED | power = med | – | 550 | 950 | – | |
| SID271 | IDD_LOW GBW | power = lo Load = 20 pF, 0.1 mA VDDA = 2.7 V | – | 150 | 350 | – | |
| SID272 | GBW_HI | power = hi | 6 | – | – | Input and output are 0.2 V to VDDA-0.2 V | |
| SID273 | GBW_MED | power = med | 3 | – | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID274 | GBW_LO IOUT_MAX | power = lo VDDA = 2.7 V, 500 mV from rail | – | 1 | – | Input and output are 0.2 V to VDDA-0.2 V | |
| SID275 | IOUT_MAX_HI | power = hi | 10 | – | – | Output is 0.5 V to VDDA -0.5 V | |
| SID276 | IOUT_MAX_MID | power = med | 10 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID277 | IOUT_MAX_LO IOUT | power = lo VDDA = 1.71 V, 500 mV from rail | – | 5 | – | Output is 0.5 V to VDDA -0.5 V | |
| SID278 | IOUT_MAX_HI | power = hi | 4 | – | – | Output is 0.5 V to VDDA -0.5 V | |
| SID279 | IOUT_MAX_MID | power = med | 4 | – | – | mA | Output is 0.5 V to VDDA-0.5 V |
| SID280 | IOUT_MAX_LO IDD_Int | power = lo Opamp block current Internal Load | – | 2 | – | Output is 0.5 V to VDDA-0.5 V | |
| SID269_I | IDD_HI_Int | power = hi | – | 1500 | 1700 | – | |
| SID270_I | IDD_MED_Int | power = med | – | 700 | 900 | μA | – |
| IDD_LOW_Int | power = lo | – | – | – | – | ||
| SID271_I | GBW | VDDA = 2.7 V | – | – | – | – | |
| SID272_I | GBW_HI_Int | power = hi General opamp specs for both internal and external modes | 8 | – | – | MHz | Output is 0.25 V to VDDA-0.25 V |
| SID281 | VIN | Charge-pump on, VDDA = 2.7 V | –0.05 | – | VDDA-0. 2 | – | |
| SID282 | VCM VOUT | Charge-pump on, VDDA = 2.7 V VDDA = 2.7 V | –0.05 | – | VDDA-0. 2 | V | – |
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID283 | VOUT_1 | power=hi, Iload=10 mA | 0.5 | – | VDDA -0.5 | – | |
| SID284 | VOUT_2 | power=hi, Iload=1 mA | 0.2 | – | VDDA -0.2 | – | |
| SID285 | VOUT_3 | power=med, Iload=1 mA | 0.2 | – | VDDA -0.2 | V | – |
| SID286 | VOUT_4 | power=lo, Iload=0.1 mA | 0.2 | – | VDDA -0.2 | – | |
| SID288 | VOS_TR | Offset voltage, trimmed | –1.0 | 0.5 | 1.0 | High mode, input 0 V to VDDA-0.2 V | |
| SID288A | VOS_TR | Offset voltage, trimmed | – | 1 | – | mV | Medium mode, input 0 V to VDDA-0.2 V |
| SID288B | VOS_TR | Offset voltage, trimmed | – | 2 | – | Low mode, input 0 V to VDDA-0.2 V | |
| SID290 | VOS_DR_TR | Offset voltage drift, trimmed | –10 | 3 | 10 | μV/°C | High mode |
| SID290A | VOS_DR_TR | Offset voltage drift, trimmed | – | 10 | – | Medium mode | |
| SID290B | VOS_DR_TR | Offset voltage drift, trimmed | – | 10 | – | μV/°C | Low mode |
| SID291 | CMRR | DC | 70 | 80 | – | Input is 0 V to VDDA-0.2 V, Output is 0.2 V to VDDA-0.2 V | |
| SID292 | PSRR Noise | At 1 kHz, 10-mV ripple | 70 | 85 | – | dB | VDDD = 3.6 V, high-power mode, input is 0.2 V to VDDA-0.2 V |
| SID294 | VN2 | Input-referred, 1 kHz, power = Hi | – | 72 | – | Input and output are at 0.2 V to VDDA-0.2 V | |
| SID295 | VN3 | Input-referred, 10 kHz, power = Hi | – | 28 | – | nV/rtHz | Input and output are at 0.2 V to VDDA-0.2 V |
| SID296 | VN4 | Input-referred, 100 kHz, power = Hi | – | 15 | – | Input and output are at 0.2 V to VDDA-0.2 V | |
| SID297 | CLOAD | Stable up to max. load. Performance specs at 50 pF. | – | – | 125 | pF | – |
| SID298 | SLEW_RATE | Cload = 50 pF, Power = High, VDDA = 2.7 V | 6 | – | – | V/μs | – |
| SID299 | T_OP_WAKE | From disable to enable, no external RC dominating | – | – | 25 | μs | – |
| SID299A | OL_GAIN COMP_MODE | Open Loop Gain Comparator mode; 50 mV drive, Trise=Tfall (approx.) | – | 90 | – | dB | |
| SID300 | TPD1 | Response time; power = hi | – | 150 | – | Input is 0.2 V to VDDA-0.2 V | |
| SID301 | TPD2 | Response time; power = med | – | 500 | – | ns | Input is 0.2 V to VDDA-0.2 V |
| SID302 | TPD3 | Response time; power = lo | – | 2500 | – | Input is 0.2 V to VDDA-0.2 V | |
| SID303 | VHYST_OP | Hysteresis | – | 10 | – | mV | – |
| SID304 | WUP_CTB | Wake-up time from Enabled to Usable | – | – | 25 | μs | – |
Table 8. CTBm Opamp Specifications (continued)
Table 8. CTBm Opamp Specifications (continued)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | ||||||
| SID269 | IDD_HI | power = hi | – | 1100 | 1850 | µA | – |
| SID270 | IDD_MED | power = med | – | 550 | 950 | µA | – |
| SID271 | IDD_LOW | power = lo | – | 150 | 350 | µA | – |
| GBW | Load = 20 pF, 0.1 mA VDDA = 2.7 V | ||||||
| SID272 | GBW_HI | power = hi | 6 | – | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID273 | GBW_MED | power = med | 3 | – | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID274 | GBW_LO | power = lo | – | 1 | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| IOUT_MAX | VDDA = 2.7 V, 500 mV from rail | ||||||
| SID275 | IOUT_MAX_HI | power = hi | 10 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID276 | IOUT_MAX_MID | power = med | 10 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID277 | IOUT_MAX_LO | power = lo | – | 5 | – | mA | Output is 0.5 V to VDDA -0.5 V |
| IOUT | VDDA = 1.71 V, 500 mV from rail | ||||||
| SID278 | IOUT_MAX_HI | power = hi | 4 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID279 | IOUT_MAX_MID | power = med | 4 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID280 | IOUT_MAX_LO | power = lo | – | 2 | – | mA | Output is 0.5 V to VDDA -0.5 V |
| IDD_Int | Opamp block current Internal Load | ||||||
| SID269_I | IDD_HI_Int | power = hi | – | 1500 | 1700 | µA | – |
| SID270_I | IDD_MED_Int | power = med | – | 700 | 900 | µA | – |
| SID271_I | IDD_LOW_Int | power = lo | – | – | – | µA | – |
| GBW | VDDA = 2.7 V | ||||||
| SID272_I | GBW_HI_Int | power = hi | 8 | – | – | MHz | Output is 0.25 V to VDDA-0.25 V |
| General opamp specs for both internal and external modes | |||||||
| SID281 | VIN | Charge-pump on, VDDA = 2.7 V | -0.05 | – | VDDA-0.2 | V | – |
| SID282 | VCM | Charge-pump on, VDDA = 2.7 V | -0.05 | – | VDDA-0.2 | V | – |
| VOUT | VDDA = 2.7 V |
Comparator
Table 9. Comparator DC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | ||||||
| SID269 | IDD_HI | power = hi | - | 1100 | 1850 | µA | - |
| SID270 | IDD_MED | power = med | - | 550 | 950 | µA | - |
| SID271 | IDD_LOW | power = lo | - | 150 | 350 | µA | - |
| GBW | Load = 20 pF, 0.1 mA VDDA = 2.7 V | ||||||
| SID272 | GBW_HI | power = hi | 6 | - | - | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID273 | GBW_MED | power = med | 3 | - | - | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID274 | GBW_LO | power = lo | - | 1 | - | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| IOUT_MAX | VDDA = 2.7 V, 500 mV from rail | ||||||
| SID275 | IOUT_MAX_HI | power = hi | 10 | - | - | mA | Output is 0.5 V to VDDA-0.5 V |
| SID276 | IOUT_MAX_MID | power = med | 10 |
Table 10. Comparator AC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | – | – | – | |||
| SID269 | IDD_HI | power = hi | – | 1100 | 1850 | μA | – |
| SID270 | IDD_MED | power = med | – | 550 | 950 | μA | – |
| SID271 | IDD_LOW | power = lo | – | 150 | 350 | μA | – |
| GBW | Load = 20 pF, 0.1 mA VDDA = 2.7 V | – | – | – | |||
| SID272 | GBW_HI | power = hi | 6 | – | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID273 | GBW_MED | power = med | 3 | – | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| SID274 | GBW_LO | power = lo | – | 1 | – | MHz | Input and output are 0.2 V to VDDA-0.2 V |
| IOUT_MAX | VDDA = 2.7 V, 500 mV from rail | – | – | – | |||
| SID275 | IOUT_MAX_HI | power = hi | 10 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID276 | IOUT_MAX_MID | power = med | 10 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID277 | IOUT_MAX_LO | power = lo | – | 5 | – | mA | Output is 0.5 V to VDDA -0.5 V |
| IOUT | VDDA = 1.71 V, 500 mV from rail | – | – | – | |||
| SID278 | IOUT_MAX_HI | power = hi | 4 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID279 | IOUT_MAX_MID | power = med | 4 | – | – | mA | Output is 0.5 V to VDDA -0.5 V |
| SID280 | IOUT_MAX_LO | power = lo | – | 2 | – | mA | Output is 0.5 V to VDDA -0.5 V |
| IDD_Int | Opamp block current Internal Load | – | – | – | |||
| SID269_I | IDD_HI_Int | power = hi | – | 1500 | 1700 | μA | – |
| SID270_I | IDD_MED_Int | power = med | – | 700 | 900 | μA | – |
| SID271_I | IDD_LOW_Int | power = lo | – | – | – | μA | – |
| GBW | VDDA = 2.7 V | – | – | – | |||
| SID272_I | GBW_HI_Int | power = hi | 8 | – | – | MHz | Output is 0.25 V to VDDA-0.25 V |
| General opamp specs for both internal and external modes | – | – | – | ||||
| SID281 | VIN | Charge-pump on, VDDA = 2.7 V | -0.05 | – | VDDA-0.2 | V | – |
| SID282 | VCM | Charge-pump on, VDDA = 2.7 V | -0.05 | – | VDDA-0.2 | V | – |
| VOUT | VDDA = 2.7 V | – | – | – |
Temperature Sensor
Table 11. Temperature Sensor Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | ||||||
| SID269 | IDD_HI | power = hi | - | 1100 | 1850 | µA | - |
| SID270 | IDD_MED | power = med | - | 550 | 950 | µA | - |
| SID271 | IDD_LOW | power = lo | - | 150 | 350 | µA | - |
| GBW | Load = 20 pF, 0.1 mA VDD A = 2.7 V | ||||||
| SID272 | GBW_HI | power = hi | 6 | - | - | MHz | Input and output are 0.2 V to VDD A-0.2 V |
| SID273 | GBW_MED | power = med | 3 | - | - | MHz | Input and output are 0.2 V to VDD A-0.2 V |
| SID274 | GBW_LO | power = lo | - | 1 | - | MHz | Input and output are 0.2 V to VDD A-0.2 V |
| IOUT_MAX | VDD A = 2.7 V, 500 mV from rail | ||||||
| SID275 | IOUT_MAX_HI | power = hi | 10 | - | - | mA | Output is 0.5 V to VDD A -0.5 V |
| SID276 | IOUT_MAX_MID | power = med | 10 | - | - | mA | Output is 0.5 V to VDD A -0.5 V |
| SID277 | IOUT_MAX_LO | power = lo | - | 5 | - | mA | Output is 0.5 V to VDD A -0.5 V |
| IOUT | VDD A = 1.71 V, 500 mV from rail | ||||||
| SID278 | IOUT_MAX_HI | power = hi | 4 | - | - | mA | Output is 0.5 V to VDD A -0.5 V |
| SID279 | IOUT_MAX_MID | power = med | 4 | - | - | mA | Output is 0.5 V to VDD A -0.5 V |
| SID280 | IOUT_MAX_LO | power = lo | - | 2 | - | mA | Output is 0.5 V to VDD A -0.5 V |
| IDD_Int | Opamp block current Internal Load | ||||||
| SID269_I | IDD_HI_Int | power = hi | - | 1500 | 1700 | µA | - |
| SID270_I | IDD_MED_Int | power = med | - | 700 | 900 | µA | - |
| SID271_I | IDD_LOW_Int | power = lo | - | - | - | µA |
SAR ADC
Table 12. SAR ADC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| IDD | Opamp block current, External load | - | 1100 | 1850 | µA | - | |
| SID269 | IDD_HI | power = hi | - | 550 | 950 | µA | - |
| SID270 | IDD_MED | power = med | - | 150 | 350 | µA | - |
| SID271 | IDD_LOW | power = lo | - | 150 |
Table 12. SAR ADC Specifications (continued)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID99 | A_OFFSET | Input offset voltage | – | – | 2 | mV | Measured with 1-V reference |
| SID100 | A_ISAR | Current consumption | – | – | 1 | mA | |
| SID101 | A_VINS | Input voltage range - single ended | VSS | – | VDDA | V | |
| SID102 | A_VIND | Input voltage range - differential | VSS | – | VDDA | V | |
| SID103 | A_INRES | Input resistance | – | – | 2.2 | KΩ | |
| SID104 | A_INCAP | Input capacitance | – | – | 10 | pF | |
| SID260 | VREFSAR SAR ADC AC Specifications | Trimmed internal reference to SAR | 1.188 | 1.2 | 1.212 | V | |
| SID106 | A_PSRR | Power supply rejection ratio | 70 | – | – | dB | |
| SID107 | A_CMRR | Common mode rejection ratio | 66 | – | – | dB | Measured at 1 V |
| SID108 | A_SAMP | Sample rate | – | – | 1 | Msps | |
| SID109 | A_SNR | Signal-to-noise and distortion ratio (SINAD) | 65 | – | – | dB | FIN = 10 kHz |
| SID110 | A_BW | Input bandwidth without aliasing | – | – | A_samp/2 | kHz | |
| SID111 | A_INL | Integral non linearity. VDD = 1.71 to 5.5, 1 Msps | –1.7 | – | 2 | LSB | VREF = 1 to VDD |
| SID111A | A_INL | Integral non linearity. VDDD = 1.71 to 3.6, 1 Msps | –1.5 | – | 1.7 | LSB | VREF = 1.71 to VDD |
| SID111B | A_INL | Integral non linearity. VDD = 1.71 to 5.5, 500 ksps | –1.5 | – | 1.7 | LSB | VREF = 1 to VDD |
| SID112 | A_DNL | Differential non linearity. VDD = 1.71 to 5.5, 1 Msps | –1 | – | 2.2 | LSB | VREF = 1 to VDD |
| SID112A | A_DNL | Differential non linearity. VDD = 1.71 to 3.6, 1 Msps | –1 | – | 2 | LSB | VREF = 1.71 to VDD |
| SID112B | A_DNL | Differential non linearity. VDD = 1.71 to 5.5, 500 ksps | –1 | – | 2.2 | LSB | VREF = 1 to VDD |
| SID113 | A_THD | Total harmonic distortion | – | – | –65 | dB | Fin = 10 kHz |
| SID261 | FSARINTREF | SAR operating speed without external reference bypass | – | – | 100 | ksps | 12-bit resolution |
CSD and IDAC
Table 13. CSD and IDAC Specifications
| SPEC ID# | Parameter | Description | Min | Typ | Max | Units | Details / Conditions |
|---|---|---|---|---|---|---|---|
| SYS.PER#3 | VDD_RIPPLE | Max allowed ripple on power supply, DC to 10 MHz | – | – | ±50 | mV | VDD > 2 V (with ripple), 25 °C TA, Sensitivity = 0.1 pF |
| SYS.PER#16 | VDD_RIPPLE_1.8 | Max allowed ripple on power supply, DC to 10 MHz | – | – | ±25 | mV | VDD > 1.75V (with ripple), 25 °C TA, Parasitic Capaci tance (CP) < 20 pF, Sensitivity ≥ 0.4 pF |
| SID.CSD.BLK | ICSD | Maximum block current | – | – | 4000 | μA | Maximum block current for both IDACs in dynamic (switching) mode including comparators, buffer, and reference generator |
| SID.CSD#15 | VREF | Voltage reference for CSD and Comparator | 0.6 | 1.2 | VDDA - 0.6 | V | VDDA – 0.6 or 4.4, whichever is lower |
| SID.CSD#15A | VREF_EXT | External Voltage reference for CSD and Comparator | 0.6 | VDDA - 0.6 | V | VDDA – 0.6 or 4.4, whichever is lower | |
| SID.CSD#16 | IDAC1IDD | IDAC1 (7-bits) block current | – | – | 1750 | μA | |
| SID.CSD#17 | IDAC2IDD | IDAC2 (7-bits) block current | – | – | 1750 | μA | |
| SID308 | VCSD | Voltage range of operation | 1.71 | – | 5.5 | V | 1.8 V ±5% or 1.8 V to 5.5 V |
| SID308A | VCOMPIDAC | Voltage compliance range of IDAC | 0.6 | – | VDDA –0.6 | V | VDDA – 0.6 or 4.4, whichever is lower |
| SID309 | IDAC1DNL | DNL | –1 | – | 1 | LSB | |
| SID310 | IDAC1INL | INL | –2 | – | 2 | LSB | INL is ±5.5 LSB for VDDA < 2 V |
| SID311 | IDAC2DNL | DNL | –1 | – | 1 | LSB | |
| SID312 | IDAC2INL | INL | –2 | – | 2 | LSB | INL is ±5.5 LSB for VDDA < 2 V |
| SID313 | SNR | Ratio of counts of finger to noise. Guaranteed by characterization | 5 | – | – | Ratio | Capacitance range of 5 to 35 pF, 0.1-pF sensitivity. All use cases. VDDA > 2 V. |
| SID314 | IDAC1CRT1 | Output current of IDAC1 (7 bits) in low range | 4.2 | – | 5.4 | μA | LSB = 37.5-nA typ |
| SID314A | IDAC1CRT2 | Output current of IDAC1(7 bits) in medium range | 34 | – | 41 | μA | LSB = 300-nA typ |
| SID314B | IDAC1CRT3 | Output current of IDAC1(7 bits) in high range | 275 | – | 330 | μA | LSB = 2.4-μA typ |
| SID314C | IDAC1CRT12 | Output current of IDAC1 (7 bits) in low range, 2X mode | 8 | – | 10.5 | μA | LSB = 75-nA typ |
| SID314D | IDAC1CRT22 | Output current of IDAC1(7 bits) in medium range, 2X mode | 69 | – | 82 | μA | LSB = 600-nA typ. |
| SID314E | IDAC1CRT32 | Output current of IDAC1(7 bits) in high range, 2X mode | 540 | – | 660 | μA | LSB = 4.8-μA typ |
| SID315 | IDAC2CRT1 | Output current of IDAC2 (7 bits) in low range | 4.2 | – | 5.4 | μA | LSB = 37.5-nA typ |
| SID315A | IDAC2CRT2 | Output current of IDAC2 (7 bits) in medium range | 34 | – | 41 | μA | LSB = 300-nA typ |
| SID315B | IDAC2CRT3 | Output current of IDAC2 (7 bits) in high range | 275 | – | 330 | μA | LSB = 2.4-μA typ |
| SID315C | IDAC2CRT12 | Output current of IDAC2 (7 bits) in low range, 2X mode | 8 | – | 10.5 | μA | LSB = 75-nA typ |
| SID315D | IDAC2CRT22 | Output current of IDAC2(7 bits) in medium range, 2X mode | 69 | – | 82 | μA | LSB = 600-nA typ |
| SID315E | IDAC2CRT32 | Output current of IDAC2(7 bits) in high range, 2X mode | 540 | – | 660 | μA | LSB = 4.8-μA typ |
| SID315F | IDAC3CRT13 | Output current of IDAC in 8-bit mode in low range | 8 | – | 10.5 | μA | LSB = 37.5-nA typ |
| Table 13. CSD and IDAC Specifications (continued) | ||
|---|---|---|
| -- | -- | --------------------------------------------------- |
| SPEC ID# | Parameter | Description | Min | Typ | Max | Units | Details / Conditions |
|---|---|---|---|---|---|---|---|
| SID315G | IDAC3CRT23 | Output current of IDAC in 8-bit mode in medium range | 69 | – | 82 | μA | LSB = 300-nA typ |
| SID315H | IDAC3CRT33 | Output current of IDAC in 8-bit mode in high range | 540 | – | 660 | μA | LSB = 2.4-μA typ |
| SID320 | IDACOFFSET | All zeroes input | – | – | 1 | LSB | Polarity set by Source or Sink. Offset is 2 LSBs for 37.5 nA/LSB mode |
| SID321 | IDACGAIN | Full-scale error less offset | – | – | ±10 | % | |
| SID322 | IDACMISMATCH1 | Mismatch between IDAC1 and IDAC2 in Low mode | – | – | 9.2 | LSB | LSB = 37.5-nA typ |
| SID322A | IDACMISMATCH2 | Mismatch between IDAC1 and IDAC2 in Medium mode | – | – | 5.6 | LSB | LSB = 300-nA typ |
| SID322B | IDACMISMATCH3 | Mismatch between IDAC1 and IDAC2 in High mode | – | – | 6.8 | LSB | LSB = 2.4-μA typ |
| SID323 | IDACSET8 | Settling time to 0.5 LSB for 8-bit IDAC | – | – | 5 | μs | Full-scale transition. No external load |
| SID324 | IDACSET7 | Settling time to 0.5 LSB for 7-bit IDAC | – | – | 5 | μs | Full-scale transition. No external load |
| SID325 | CMOD | External modulator capacitor. | – | 2.2 | – | nF | 5-V rating, X7R or NP0 cap |
10-bit CapSense ADC
Table 14. 10-bit CapSense ADC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| I_DD | Opamp block current, External load | ||||||
| SID269 | I_DD_HI | power = hi | – | 1100 | 1850 | µA | – |
| SID270 | I_DD_MED | power = med | – | 550 | 950 | µA | – |
| SID271 | I_DD_LOW | power = lo | – | 150 | 350 | µA | – |
| G_BW | Load = 20 pF, 0.1 mA V_DDA = 2.7 V | ||||||
| SID272 | G_BW_HI | power = hi | 6 | – | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| SID273 | G_BW_MED | power = med | 3 | – | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| SID274 | G_BW_LO | power = lo | – | 1 | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| I_OUT_MAX | V_DDA = 2.7 V, 500 mV from rail | ||||||
| SID275 | I_OUT_MAX_HI | power = hi | 10 | – | – | mA | Output is 0.5 V to V_DDA -0.5 V |
| SID276 | I_OUT_MAX_MID | power = med | 10 | – | – | mA | Output is 0.5 V to V_DDA -0.5 V |
| SID277 | I_OUT_MAX_LO | power = lo | – | 5 | – | mA | Output is 0.5 V to V_DDA |
Table 14. 10-bit CapSense ADC Specifications (continued)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| I_DD | Opamp block current, External load | – | – | – | – | – | |
| SID269 | I_DD_HI | power = hi | – | 1100 | 1850 | µA | – |
| SID270 | I_DD_MED | power = med | – | 550 | 950 | µA | – |
| SID271 | I_DD_LOW | power = lo | – | 150 | 350 | µA | – |
| G_BW | Load = 20 pF, 0.1 mA V_DDA = 2.7 V | – | – | – | – | – | |
| SID272 | G_BW_HI | power = hi | 6 | – | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| SID273 | G_BW_MED | power = med | 3 | – | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| SID274 | G_BW_LO | power = lo | – | 1 | – | MHz | Input and output are 0.2 V to V_DDA-0.2 V |
| I_OUT_MAX | V_DDA = 2.7 V, 500 mV from rail | – | – | – | – | – | |
| SID275 | I_OUT_MAX_HI | power = hi | 10 | – | – | mA | Output is 0.5 V to V_DDA -0.5 V |
| SID276 | I_OUT_MAX_MID | power = med | 10 | – | – | mA | Output is 0.5 V to V_DDA -0.5 V |
| SID277 | I_OUT_MAX_LO | power = lo | – | 5 | – | mA | Output is 0.5 V to V_DDA -0.5 V |
| I_OUT | V_DDA = 1.71 V, 500 mV from rail | – | – | – | – |
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 15. TCPWM Specifications
| Spec ID | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID.TCPWM.1 | ITCPWM1 | Block current consumption at 3 MHz | – | – | 45 | μA | All modes (TCPWM) |
| SID.TCPWM.2 | ITCPWM2 | Block current consumption at 12 MHz | – | – | 155 | μA | All modes (TCPWM) |
| SID.TCPWM.2A | ITCPWM3 | Block current consumption at 48 MHz | – | – | 650 | μA | All modes (TCPWM) |
| SID.TCPWM.3 | TCPWMFREQ | Operating frequency | – | – | Fc | MHz | Fc max = CLK_SYS Maximum = 48 MHz |
| SID.TCPWM.4 | TPWMENEXT | Input trigger pulse width | 2/Fc | – | – | – | For all trigger events[7] |
| SID.TCPWM.5 | TPWMEXT | Output trigger pulse widths | 2/Fc | – | – | ns | Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs |
| SID.TCPWM.5A | TCRES | Resolution of counter | 1/Fc | – | – | ns | Minimum time between successive counts |
| SID.TCPWM.5B | PWMRES | PWM resolution | 1/Fc | – | – | ns | Minimum pulse width of PWM Output |
| SID.TCPWM.5C | QRES | Quadrature inputs resolution | 1/Fc | – | – | ns | Minimum pulse width between Quadrature phase inputs |
I 2C
Table 16. Fixed I2C DC Specifications[7]
| Spec ID | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID149 | I2C1 | Block current consumption at 100 kHz | – | – | 50 | μA | – |
| SID150 | I2C2 | Block current consumption at 400 kHz | – | – | 135 | μA | – |
| SID151 | I2C3 | Block current consumption at 1 Mbps | – | – | 310 | μA | – |
| SID152 | I2C4 | I²C enabled in Deep Sleep mode | – | 1 | – | μA | – |
Table 17. Fixed I2C AC Specifications[7]
| Spec ID | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID153 | I2C1 | Bit rate | – | – | 1 | Msps | – |
SPI
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID1 | VDDD_ABS | Digital supply relative to VSS | –0.5 | – | 6 | – | |
| SID2 | VCCD_ABS | Direct digital core voltage input relative to VSS | –0.5 | – | 1.95 | V | – |
| SID3 | VGPIO_ABS | GPIO voltage | –0.5 | – | VDD+0.5 | – | |
| SID4 | IGPIO_ABS | Maximum current per GPIO | –25 | – | 25 | mA | – |
| SID5 | IGPIO_injection | GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS | –0.5 | – | 0.5 | mA | Current injected per pin |
| BID44 | ESD_HBM | Electrostatic discharge human body model | 2200 | – | – | V | – |
| BID45 | ESD_CDM | Electrostatic discharge charged device model | 500 | – | – | V | – |
| BID46 | LU | Pin current for latch-up | –140 | – | 140 | mA | – |
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/ Conditions |
|---|---|---|---|---|---|---|---|
| SID53 | VDD | Power supply input voltage | 1.8 | – | 5.5 | Internally regulated supply | |
| SID255 | VDD | Power supply input voltage (VCCD = VDDD = VDDA) | 1.71 | – | 1.89 | V | Internally unregulated supply |
| SID54 | VCCD | Output voltage (for core logic) | – | 1.8 | – | – | |
| SID55 | CEFC | External regulator voltage (VCCD) bypass | – | 0.1 | – | X5R ceramic or better | |
| SID56 | CEXC | Power supply bypass capacitor | – | 1 | – | μF | X5R ceramic or better |
| Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C. | |||||||
| SID10 | IDD5 | Execute from flash; CPU at 6 MHz | – | 1.8 | 2.4 | mA | |
| SID16 | IDD8 | Execute from flash; CPU at 24 MHz | – | 3.0 | 4.6 | mA | |
| SID19 | IDD11 | Execute from flash; CPU at 48 MHz | – | 5.4 | 7.1 | mA | |
| Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) | |||||||
| SID22 | IDD17 | I²C wakeup WDT, and Comparators on | – | 1.1 | 1.8 | mA | 6 MHZ |
| SID25 | IDD20 | I²C wakeup, WDT, and Comparators on | – | 1.5 | 2.1 | mA | 12 MHZ |
| Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) |
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID1 | VDD_ABS | Digital supply relative to VSS | –0.5 | – | 6 | V | – |
| SID2 | VCCD_ABS | Direct digital core voltage input relative to VSS | –0.5 | – | 1.95 | V | – |
| SID3 | VGPIO_ABS | GPIO voltage | –0.5 | – | VDD+0.5 | V | – |
| SID4 | IGPIO_ABS | Maximum current per GPIO | –25 | – | 25 | mA | – |
Table 3. AC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID48 | FCPU | CPU frequency | DC | – | 48 | MHz | 1.71 ≤ VDD ≤ 5.5 |
| SID49[2] | TSLEEP | Wakeup from Sleep mode | – | 0 | – | μs | |
| SID50[2] | TDEEPSLEEP | Wakeup from Deep Sleep mode | – | 35 | – | μs |
GPIO
Table 4. GPIO DC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID57 | VIH[3] | Input voltage high threshold | 0.7 VDDD | – | – | CMOS Input | |
| SID58 | VIL | Input voltage low threshold | – | – | 0.3 VDDD | CMOS Input | |
| SID241 | VIH[3] | LVTTL input, VDDD < 2.7 V | 0.7 VDDD | – | – | – | |
| SID242 | VIL | LVTTL input, VDDD < 2.7 V | – | – | 0.3 VDDD | – | |
| SID243 | VIH[3] | 2.7 V LVTTL input, VDDD | 2.0 | – | – | – | |
| SID244 | VIL | 2.7 V LVTTL input, VDDD | – | – | 0.8 | V | – |
| SID59 | VOH | Output voltage high level | VDDD –0.6 | – | – | IOH = 4 mA at 3 V VDDD | |
| SID60 | VOH | Output voltage high level | VDDD –0.5 | – | – | IOH = 1 mA at 1.8 V VDDD | |
| SID61 | VOL | Output voltage low level | – | – | 0.6 | IOL = 4 mA at 1.8 V VDDD | |
| SID62 | VOL | Output voltage low level | – | – | 0.6 | IOL = 10 mA at 3 V VDDD | |
| SID62A | VOL | Output voltage low level | – | – | 0.4 | IOL = 3 mA at 3 V VDDD | |
| SID63 | RPULLUP | Pull-up resistor | 3.5 | 5.6 | 8.5 | kΩ | – |
| SID64 | RPULLDOWN | Pull-down resistor | 3.5 | 5.6 | 8.5 | – | |
| SID65 | IIL | Input leakage current (absolute value) | – | – | 2 | nA | 25 °C, VDDD = 3.0 V |
| SID66 | CIN | Input capacitance | – | – | 7 | pF | – |
| SID67[4] | VHYSTTL | Input hysteresis LVTTL | 25 | 40 | – | VDDD 2.7 V | |
| SID68[4] | VHYSCMOS | Input hysteresis CMOS | 0.05 × VDDD | – | – | mV | VDD < 4.5 V |
| SID68A[4] | VHYSCMOS5V5 | Input hysteresis CMOS | 200 | – | – | VDD > 4.5 V | |
| SID69[4] | IDIODE | Current through protection diode to VDD/VSS | – | – | 100 | μA | – |
| SID69A[4] | ITOT_GPIO | Maximum total source or sink chip current | – | – | 200 | mA | – |
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID28 | IDD23 | I²C wakeup, WDT, and Comparators on | – | 1.1 | 1.8 | mA | 6 MHZ |
| SID28A | IDD23A | I²C wakeup, WDT, and Comparators on | – | 1.5 | 2.1 | mA | 12 MHZ |
| SID30 | IDD25 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 40 | µA | T = –40 °C to 60 °C |
| SID31 | IDD26 | I²C wakeup and WDT on | – | 2.5 | 125 | µA | Max is at 3.6 V and 85 °C |
| SID33 | IDD28 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 40 | µA | T = –40 °C to 60 °C |
| SID34 | IDD29 | I²C wakeup and WDT on | – | 2.5 | 125 | µA | Max is at 5.5 V and 85 °C |
| SID36 | IDD31 | I²C wakeup and WDT on; T = –40 °C to 60 °C | – | 2.5 | 60 | µA | T = –40 °C to 60 °C |
| SID37 | IDD32 | I²C wakeup and WDT on | – | 2.5 | 180 | µA | Max is at 1.89 V and 85 °C |
| SID307 | IDD_XR | Supply current while XRES asserted | – | 2 | 5 | mA | – |
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID48 | FCPU | CPU frequency | DC | – | 48 | MHz | 1.71 ≤ VDD ≤ 5.5 |
| SID49[2] | TSLEEP | Wakeup from Sleep mode | – | 0 | – | µs | – |
| SID50[2] | TDEEPSLEEP | Wakeup from Deep Sleep mode | – | 35 | – | µs | – |
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Table 5. GPIO AC Specifications (continued)
(Guaranteed by Characterization)
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID70 | TRISEF | Rise time in fast strong mode | 2 | – | 12 | ns | 3.3 V VDDD, Cload = 25 pF |
| SID71 | TFALLF | Fall time in fast strong mode | 2 | – | 12 | ns | 3.3 V VDDD, Cload = 25 pF |
| SID72 | TRISES | Rise time in slow strong mode | 10 | – | 60 | ns | 3.3 V VDDD, Cload |
XRES
Table 6. XRES DC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID57 | V_IH[3] | Input voltage high threshold | 0.7 × V_DDD | – | – | V | CMOS Input |
| SID58 | V_IL | Input voltage low threshold | – | – | 0.3 × V_DDD | V | CMOS Input |
| SID241 | V_IH[3] | LVTTL input, V_DDD < 2.7 V | 0.7 × V_DDD | – | – | V | – |
| SID242 | V_IL | LVTTL input, V_DDD < 2.7 V | – | – | 0.3 × V_DDD | V | – |
| SID243 | V_IH[3] | LVTTL input, V_DDD ≥ 2.7 V | 2.0 | – | – | V | – |
| SID244 | V_IL | LVTTL input, V_DDD ≥ 2.7 V | – | – | 0.8 | V | – |
| SID59 | V_OH | Output voltage high level | V_DDD – 0.6 | – | – | V | I_OH = |
Table 7. XRES AC Specifications
| Spec ID# | Parameter | Description | Min | Typ | Max | Units | Details/Conditions |
|---|---|---|---|---|---|---|---|
| SID83[5] | TRESETWIDTH | Reset pulse width | 1 | – | – | μs | – |
| BID194[5] | TRESETWAKE | Wake-up time from reset release | – | – | 2.7 | ms | – |
Thermal Information
| Parameter | Description | Package | Min | Typ | Max | Units |
|---|---|---|---|---|---|---|
| TA | Operating ambient temperature | – | –40 | 25 | 105 | °C |
| TJ | Operating junction temperature | – | –40 | – | 125 | °C |
| TJA | Package θJA | 44-pin TQFP | – | 55.6 | – | °C/Watt |
| TJC | Package θJC | 44-pin TQFP | – | 14.4 | – | °C/Watt |
| TJA | Package θJA | 64-pin TQFP (0.5-mm pitch) | – | 46 | – | °C/Watt |
| TJC | Package θJC | 64-pin TQFP (0.5-mm pitch) | – | 10 | – | °C/Watt |
| TJA | Package θJA | 64-pin TQFP (0.8-mm pitch) | – | 36.8 | – | °C/Watt |
| TJC | Package θJC | 64-pin TQFP (0.8-mm pitch) | – | 9.4 | – | °C/Watt |
| TJA | Package θJA | 48-pin TQFP (0.5-mm pitch) | – | 39.4 | – | °C/Watt |
| TJC | Package θJC | 48-pin TQFP (0.5-mm pitch) | – | 9.3 | – | °C/Watt |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| CY8C4146AXI | now Infineon | — |
| CY8C4146AXI-S443 | now Infineon | — |
| CY8C4146AXI-S445 | now Infineon | — |
| CY8C4146AXI-S453 | now Infineon | — |
| CY8C4146AXI-S455 | now Infineon | — |
| CY8C4146AZI-S445 | now Infineon | — |
| CY8C4146AZI-S453 | now Infineon | — |
| CY8C4146AZI-S455 | now Infineon | — |
| CY8C4146AZI-S463 | now Infineon | — |
| CY8C4146AZQ-S445 | now Infineon | — |
| CY8C4146AZQ-S455 | now Infineon | — |
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