TPSM53602
The TPSM53602 is an electronic component from Texas Instruments. View the full TPSM53602 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Texas Instruments
Category
Voltage Regulators - Switching
Overview
The TPSM53602 power module is a highly integrated 2-A power solution that combines a 36-V input, stepdown, DC/DC converter with power MOSFETs, a shielded inductor, and passives in a thermallyenhanced QFN package. The 5-mm x 5.5-mm x 4mm, 15-pin package uses Enhanced HotRod QFN technology for improved thermal performance, small footprint, and low EMI. The package footprint has all pins accessible from the perimeter and a single large thermal pad for simple layout and easy handling in manufacturing.
The total solution requires as few as four external and magnetics part selection from the design process.
components and eliminates the loop compensation The full feature set includes power good, programmable UVLO, prebias start-up, overcurrent, and overtemperature protections, making the TPSM53602 an excellent device for powering a wide range of applications.
Features
- 5-mm × 5.5-mm × 4-mm Enhanced HotRod QFN package
- -85-mm 2 solution size (single sided)
- -Low EMI: Meets CISPR11 radiated emissions
- -Excellent thermal performance: Up to 14 W output power at 85°C, no airflow
- -Standard footprint: single large thermal pad and all pins accessible from perimeter
- Input voltage range: 3.8 V to 36 V
- Output voltage range: 1 V to 7 V
- Efficiency up to 95%
- Power-good flag
- Precision enable
- Built-in hiccup-mode short-circuit protection, overtemperature protection, start-up into pre-bias output, soft start, and UVLO
- Operating IC junction range: -40°C to +125°C
- Operating ambient range: -40°C to +105°C
- Shock and vibration tested to Mil-STD-883D
- Pin compatible with: 3-A TPSM53603 and 4-A TPSM53604
- Create a custom design using the TPSM53602 with the WEBENCH ® Power Designer
- Download the EVM Design Files for fast board design
Applications
Pin Configuration
Figure 5-1. RDA Package 15-Pin QFN Top View
Electrical Characteristics
Limits apply over T A = -40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, I OUT = IOUT maximum, (unless otherwise noted); CIN1 = 2x10 μF, 50-V, 1206 ceramic; C IN2 = 100 nF, 50-V, 0603 ceramic; C OUT = 3x22 μF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) | INPUT VOLTAGE (V IN ) |
| V | Input voltage range | Over I OUT range | 3.8 (1) | 36 | V | |
| IN | V IN turn on | V IN increasing, I OUT = 0 A | 3.55 | V | ||
| V | V IN turn off | V IN decreasing, I OUT = 0 A | 3.05 | V | ||
| I Q | Quiescient current | Non-switching, V FB = 1.2 V | 24 | μA | ||
| I SHDN | Shutdown supply current | V EN = 0 V, I OUT = 0 A | 5 | 10 | μA | |
| INTERNAL LDO (V5V) | INTERNAL LDO (V5V) | INTERNAL LDO (V5V) | INTERNAL LDO (V5V) | INTERNAL LDO (V5V) | INTERNAL LDO (V5V) | INTERNAL LDO (V5V) |
| V5V | Internal LDO output voltage appearing at the V5V pin | 6 V ≤ V IN ≤ 36 V | 4.75 | 5 | 5.25 | V |
| FEEDBACK | FEEDBACK | FEEDBACK | FEEDBACK | FEEDBACK | FEEDBACK | FEEDBACK |
| V FB | Feedback voltage (2) | -40°C ≤ T J ≤ +125°C, I OUT = 0.75 A | 0.985 | 1 | 1.015 | V |
| V FB | Load regulation | T A = +25°C, 0.5 A ≤ I OUT ≤ 2 A | 0.06 | % | ||
| V FB | Line regulation | T A = +25°C, I OUT = 0.75 A, Over V IN range | 0.15 | % | ||
| I FB | Current into FB pin | FB = 1 V | 0.2 | 50 | nA | |
| CURRENT | CURRENT | CURRENT | CURRENT | CURRENT | CURRENT | CURRENT |
| I OUT | Output current | T A = 25°C | 0 | 2 | A | |
| I OUT | Over-current threshold | 3.5 | A | |||
| V HC | FB pin voltage required to trip short- circuit hiccup mode | 0.4 | V | |||
| t HC | Time between current-limit hiccup burst | 94 | ms | |||
| ENABLE (EN PIN) | ENABLE (EN PIN) | ENABLE (EN PIN) | ENABLE (EN PIN) | ENABLE (EN PIN) | ENABLE (EN PIN) | ENABLE (EN PIN) |
| V EN-VCC-H | EN input level required to turn on internal LDO | Rising threshold | 1 | V | ||
| V EN-VCC-L | EN input level required to turn off internal LDO | Falling threshold | 0.3 | V | ||
| V EN-H | EN input level required to start switching | Rising threshold | 1.2 | 1.23 | 1.26 | V |
Limits apply over T A = -40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, I OUT = IOUT maximum, (unless otherwise noted); CIN1 = 2x10 μF, 50-V, 1206 ceramic; C IN2 = 100 nF, 50-V, 0603 ceramic; C OUT = 3x22 μF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| V EN-HYS | Hysteresis below V EN-H | Falling | 100 | mV | ||
| I LKG-EN | Enable input leakage current | V EN = 3.3 V | 0.2 | nA | ||
| POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) | POWER GOOD (PGOOD PIN) |
| V PG-HIGH-UP | V OUT rising (fault) | %of FB voltage | 107 | % | ||
| V PG-HIGH-DN | V OUT falling (good) | %of FB voltage | 105 | % | ||
| V PG-LOW-UP | V OUT rising (good) | %of FB voltage | 94 | % | ||
| V PG-LOW-DN | V OUT falling (fault) | %of FB voltage | 92 | % | ||
| R PG | Power-good flag R DSON | V EN = 0 V | 35 | Ω | ||
| V IN-PG | Minimum input voltage for proper PGOOD function | 50-μA, EN = 0 V | 2 | V | ||
| V PG | PGOOD logic low output | 50-μA, EN = 0 V, V IN = 2 V | 0.2 | V | ||
| PERFORMANCE | PERFORMANCE | PERFORMANCE | PERFORMANCE | PERFORMANCE | PERFORMANCE | PERFORMANCE |
| η | Efficiency | I OUT = 2 A, T A = 25°C | 91 | % | ||
| SOFT START | SOFT START | SOFT START | SOFT START | SOFT START | SOFT START | SOFT START |
| t SS | Internal soft-start time | 4 | ms | |||
| SWITCHING FREQUENCY | SWITCHING FREQUENCY | SWITCHING FREQUENCY | SWITCHING FREQUENCY | SWITCHING FREQUENCY | SWITCHING FREQUENCY | SWITCHING FREQUENCY |
| ƒ SW-MAX | Max switching frequency | I OUT = 2 A, T A = 25°C | 1.4 (3) | MHz |
Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
| PARAMETER | PARAMETER | MIN | MAX | UNIT |
|---|---|---|---|---|
| Input voltage | VIN to PGND | -0.3 | 38 | V |
| Input voltage | EN to AGND (2) | -0.3 | V IN + 0.3 | V |
| Input voltage | PGOOD to AGND (2) | -0.3 | 22 | V |
| Input voltage | FB to AGND | -0.3 | 5.5 | V |
| Input voltage | AGND to PGND | -0.3 | 0.3 | V |
| Output voltage | VOUT to PGND (2) | -0.3 | V IN + 0.3 | V |
| Output voltage | V5V to AGND | 0 | 5.5 | V |
| Operating IC junction temperature, T J (3) | Operating IC junction temperature, T J (3) | -40 | 150 | °C |
| Storage temperature, T stg | Storage temperature, T stg | -55 | 150 | °C |
| Peak reflow case temperature | Peak reflow case temperature | 245 | °C | |
| Maximum number or reflows allowed | Maximum number or reflows allowed | 3 | ||
| Mechanical vibration | Mil-STD-883D, Method 2007.2, 20 to 2000 Hz | 20 | G | |
| Mechanical shock | Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted | 500 | G |
- (3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the module is never exceeded.
Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted) (1)
| MIN | MAX | UNIT | |
|---|---|---|---|
| Input voltage, V IN | 3.8 (3) | 36 | V |
| Output voltage, V OUT | 1 | 7 (4) | V |
| Output current, I OUT | 0 | 2 | A |
| EN voltage, V EN (2) | 0 | V IN | V |
| PGOOD pullup voltage, V PGOOD (2) | 0 | 18 | V |
| PGOOD sink current | 3 | mA | |
| Operating ambient temperature, T A | -40 | 105 | °C |
| Input capacitance, C IN (5) | 20 | μF | |
| Output capacitance, C OUT | min (6) | 1000 | μF |
Thermal Information
| THERMAL METRIC (1) | THERMAL METRIC (1) | TPSM53602 RDA (QFN) 15 PINS | UNIT |
|---|---|---|---|
| R θJA | Junction-to-ambient thermal resistance (2) | 19.5 | °C/W |
| ψ JT | Junction-to-top characterization parameter (3) | 1 | °C/W |
| ψ JB | Junction-to-board characterization parameter (4) | 5.5 | °C/W |
| T SHDN | Thermal shutdown temperature | 165 | °C |
| T SHDN | Recovery temperaure | 148 | °C |
Typical Application
The TPSM53602 is a synchronous, step-down, DC/DC power module. It is used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 2 A. The TPSM53602 can be configured in a negative output voltage, inverting buck-boost (IBB) topology. For more details, see the Negative Output Voltage using the TPSM53602/3/4 application note. The following design procedure can be used to select components for the TPSM53602. Alternately, the WEBENCH ® software can be used to generate complete designs. When generating a design, the WEBENCH ® software uses an iterative design procedure and accesses comprehensive databases of components. See www.ti.com for more details.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| TPSM53602/3/4 | Texas Instruments | — |
| TPSM53602RDAR | Texas Instruments | 15-PowerBQFN Module |
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