TLV320AIC3204S

Power up the MDAC divider with value 4 w 30 0c 84 # Program the OSR of DAC to 64 w 30 0d 00 w 30 0e 40 # Set the DAC Mode to PRB_P8 w 30 3c 08 # Select Page 1 w 30 00 01 # Disable Internal Crude AVdd in presence of external AVdd supply or before # powering up internal AVdd LDO w 30 01 08 # Enable Master Analog Power Control w 30 02 00 # Set the REF charging time to 40ms w 30 7b 01 # HP soft stepping settings for optimal pop performance at power up # Rpop used is 6k with N = 6 & soft step = 20usec. This should work with 47μF coupling # capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs 'pop' sound. w 30 14 25 # Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to # Input Common Mode w 30 0a 00 # Route Left DAC to HPL w 30 0c 08 # Route Right DAC to HPR w 30 0d 08 # Set the DAC PTM mode to PTM_P1 w 30 03 08 w 30 04 08 # Set the HPL gain to 0dB w 30 10 00 # Set the HPR gain to 0dB w 30 11 00 # Power up HPL and HPR drivers w 30 09 30 # Wait for 2.5 sec for soft stepping to take effect # Else read Page 1, Register 63d, D(7:6). When = '11' soft-stepping is complete # Select Page 0 w 30 00 00 # Power up the Left and Right DAC Channels with route the Left Audio digital data to # Left Channel DAC and Right Audio digital data to Right Channel DAC w 30 3f d6 # Unmute the DAC digital volume control w 30 40 00

Stereo Audio Codec

The TLV320AIC3204S is a stereo audio codec from Texas Instruments. Power up the MDAC divider with value 4 w 30 0c 84 # Program the OSR of DAC to 64 w 30 0d 00 w 30 0e 40 # Set the DAC Mode to PRB_P8 w 30 3c 08 # Select Page 1 w 30 00 01 # Disable Internal Crude AVdd in presence of external AVdd supply or before # powering up internal AVdd LDO w 30 01 08 # Enable Master Analog Power Control w 30 02 00 # Set the REF charging time to 40ms w 30 7b 01 # HP soft stepping settings for optimal pop performance at power up # Rpop used is 6k with N = 6 & soft step = 20usec. This should work with 47μF coupling # capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs 'pop' sound. w 30 14 25 # Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to # Input Common Mode w 30 0a 00 # Route Left DAC to HPL w 30 0c 08 # Route Right DAC to HPR w 30 0d 08 # Set the DAC PTM mode to PTM_P1 w 30 03 08 w 30 04 08 # Set the HPL gain to 0dB w 30 10 00 # Set the HPR gain to 0dB w 30 11 00 # Power up HPL and HPR drivers w 30 09 30 # Wait for 2.5 sec for soft stepping to take effect # Else read Page 1, Register 63d, D(7:6). When = '11' soft-stepping is complete # Select Page 0 w 30 00 00 # Power up the Left and Right DAC Channels with route the Left Audio digital data to # Left Channel DAC and Right Audio digital data to Right Channel DAC w 30 3f d6 # Unmute the DAC digital volume control w 30 40 00. View the full TLV320AIC3204S datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Key Specifications

Parameter	Value
Data Interface	Serial
Dynamic Range, ADCs / DACs (db) Typ	92 / 100
Mounting Type	Surface Mount
Number of ADCs / DACs	2 / 2
Operating Temperature	-40°C ~ 85°C
Package / Case	32-VFQFN Exposed Pad
Resolution (Bits)	32 b
S/N Ratio, ADCs / DACs (db) Typ	93 / 100
Sigma Delta	Yes
Supplier Device Package	32-VQFN (5x5)
Type	Stereo Audio
Analog Supply Voltage	1.5V ~ 1.95V
Voltage - Supply, Digital	1.26V ~ 1.95V

Overview

Part: TLV320AIC3204 — Texas Instruments

Type: Stereo Audio Codec

Description: A flexible, low-power, low-voltage stereo audio codec with programmable inputs and outputs, PowerTune capabilities, fixed and parameterizable signal processing blocks, integrated PLL, integrated LDOs, and flexible digital interfaces.

Operating Conditions:

Supply voltage: 1.5–1.95 V (AVdd), 1.26–1.95 V (DVdd), 1.1–3.6 V (IOVDD), 1.9–3.6 V (LDOIN)
Operating temperature: -40 to 85 °C
PLL input frequency: 0.512–20 MHz
Master Clock Frequency: up to 50 MHz (DVdd ≥ 1.65V)

Absolute Maximum Ratings:

Max supply voltage: 2.2 V (AVdd, DVdd), 3.9 V (IOVDD, LDOIN)
Max junction/storage temperature: 105 °C (junction), 125 °C (storage)

Key Specs:

Stereo Audio DAC SNR: 100 dB
Stereo Audio ADC SNR: 93 dB (A-weighted, 48kHz, AVdd=1.8V)
ADC THD+N: -85 dB (A-weighted, -3dBFS, 1kHz, 48kHz, AVdd=1.8V)
DAC Playback Power: 4.1 mW (Stereo 48ksps)
ADC Record Power: 6.1 mW (Stereo 48ksps)
Headphone Output Load Resistance: 14.4 Ω (single-ended), 24.4 Ω (differential)
Microphone Bias Current Sourcing: 3 mA (Mode 2), 140 mA (Mode 3)
I2C/SPI Clock Frequency: up to 400 kHz (SCL)

Features:

PowerTune™ technology
Extensive Signal Processing Options
Six Single-Ended or 3 Fully-Differential Analog Inputs
Stereo Analog and Digital Microphone Inputs
Stereo Headphone Outputs
Stereo Line Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
Programmable PLL
Integrated LDO

Applications:

Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing

Package:

32-pin QFN (5 mm x 5 mm)

Features

Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps DAC Playback
Stereo Audio ADC with 93dB SNR
6.1mW Stereo 48ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Six Single-Ended or 3 Fully-Differential Analog Inputs
Stereo Analog and Digital Microphone Inputs
Stereo Headphone Outputs
Stereo Line Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
Programmable PLL
Integrated LDO
5 mm x 5 mm 32-pin QFN Package
1.2 Applications
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing

Applications

TI E2E Community Home Page

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Pin Configuration

Figure 2-1. QFN (RHB) Package, Bottom View

SLOS602A-SEPTEMBER 2008-REVISED OCTOBER 2008

Electrical Characteristics

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
AUDIOADC	(1) (2)
Input signal level (0dB)	Input signal level (0dB)	Single-ended, CM = 0.9V		0.5		V RMS
Device Setup	Device Setup	1kHz sine wave input Single-ended Configuration IN1R to Right ADC and IN1L to Left ADC, R in = 20K, f s = 48kHz, AOSR = 128, MCLK = 256*f s , PLL Disabled; AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1, Power Tune = PTM_R4 Inputs ac-shorted to ground	80	93		dB
SNR Signal-to-noise ratio, A-weighted (1)	(2)	IN2R, IN3R routed to Right ADC and ac-shorted to ground IN2L, IN3L routed to Left ADC and ac-shorted to ground		93
DR Dynamic range A-weighted	(1) (2)	-60dB full-scale, 1-kHz input signal		92		dB
		-3 dB full-scale, 1-kHz input signal		-85	-70	dB
THD+N Total Harmonic Distortion plus Noise	THD+N Total Harmonic Distortion plus Noise	IN2R,IN3R routed to Right ADC IN2L, IN3L routed to Left ADC -3dB full-scale, 1-kHz input signal		-85
AUDIO ADC	AUDIO ADC
	Input signal level (0dB)	Single-ended, CM=0.75V, AVdd = 1.5V		0.375		V RMS
Device Setup	Device Setup	1kHz sine wave input Single-ended Configuration IN1R, IN2R, IN3R routed to Right ADC IN1L, IN2L, IN3L routed to Left ADC R in = 20K, f s = 48kHz, AOSR=128, MCLK = 256* f s , PLL Disabled, AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1 Power Tune = PTM_R4
SNR	Signal-to-noise ratio, A-weighted (1) (2)	Inputs ac-shorted to ground		91		dB
DR	Dynamic range A-weighted (1) (2)	-60dB full-scale, 1-kHz input signal		90		dB
THD+N	Total Harmonic Distortion plus Noise	-3dB full-scale, 1-kHz input signal		-80		dB
AUDIO ADC	AUDIO ADC
	Input signal level (0dB)	Differential Input, CM=0.9V		10		mV
Device Setup	Device Setup	1kHz sine wave input Differential configuration IN1L and IN1R routed to Right ADC IN2L and IN2R routed to Left ADC R in =10K, f s =48kHz, AOSR=128 MCLK = 256* f s PLL Disabled AGC = OFF, Channel Gain=40dB Processing Block = PRB_R1, Power Tune = PTM_R4
ICN	Idle-Channel Noise, A-weighted (1) (2)	Inputs ac-shorted to ground, input referred noise		2		μ V RMS

SLOS602A-SEPTEMBER 2008-REVISED OCTOBER 2008

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

PARAMETER	TEST CONDITIONS	TYP	UNIT
AUDIO ADC
Gain Error	1kHz sine wave input Single-ended configuration R in = 20K f s = 48kHz, AOSR=128, MCLK = 256* f s , PLL Disabled AGC = OFF, Channel Gain=0dB Processing Block = PRB_R1, Power Tune = PTM_R4, CM=0.9V	-0.05	dB
Input Channel Separation	1kHz sine wave input at -3dBFS Single-ended configuration IN1L routed to Left ADC IN1R routed to Right ADC, R in = 20K AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V	108	dB
Input Pin Crosstalk	1kHz sine wave input at -3dBFS on IN2L, IN2L internally not routed. IN1L routed to Left ADC ac-coupled to ground 1kHz sine wave input at -3dBFS on IN2R, IN2R internally not routed. IN1R routed to Right ADC ac-coupled to ground Single-ended configuration R in = 20K, AOSR=128 Channel, Gain=0dB, CM=0.9V	115	dB
PSRR	217Hz, 100mVpp signal on AVdd, Single-ended configuration, Rin=20K, Channel Gain=0dB; CM=0.9V	55	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 10K, PGA gain set to 0dB	0	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 10K, PGA gain set to 47.5dB	47.5	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 20K, PGA gain set to 0dB	-6	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 20K, PGA gain set to 47.5dB	41.5	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 40K, PGA gain set to 0dB	-12	dB
ADC programmable gain amplifier gain	Single-Ended, Rin = 40K, PGA gain set to 47.5dB	35.5	dB
ADC programmable gain amplifier step size	1-kHz tone	0.5	dB

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE	ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE	ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE	ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE	ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE	ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Device	Setup	Load = 16 Ω (single-ended), 50pF; Input and Output CM=0.9V; Headphone Output on LDOIN Supply; IN1L routed to HPL and IN1R routed to HPR; Channel Gain=0dB
Gain	Error		-0.8		dB
Noise,	A-weighted (1)	Idle Channel, IN1L and IN1R ac-shorted to ground	3		μ V RMS
THD	Total Harmonic Distortion	446mVrms, 1-kHz input signal	-89		dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE	ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE Device Setup	ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE Load = 10KOhm (single-ended), 56pF; Input and Output CM=0.9V; LINE Output on LDOIN Supply; IN1L routed to ADCPGA_L and IN1R routed to ADCPGA_R; Rin = 20k ADCPGA_L routed to LOL and ADCPGA_R routed to LOR; Channel Gain = 0dB	ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE	ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE	ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
	Gain Error		0.6		dB
Noise,	A-weighted (1)	Idle Channel, IN1L and IN1R ac-shorted to ground	7		μ V RMS
Noise,	A-weighted (1)	Channel Gain=40dB, Input Signal (0dB) = 5mV rms Inputs ac-shorted to ground, Input Referred	3.4		μ V RMS
MICROPHONE BIAS	MICROPHONE BIAS	MICROPHONE BIAS	MICROPHONE BIAS	MICROPHONE BIAS	MICROPHONE BIAS
Output	Bias voltage	Bias voltage CM=0.9V, LDOin = 3.3V
	Micbias Mode 0, Connect	to AVdd or LDOin	1.25		V
	Micbias Mode 1, Connect to	LDOin	1.7		V
	Micbias Mode 2,	Connect to LDOin 2.5			V
	Micbias Mode 3, Connect to AVdd	AVdd			V
	Micbias Mode 3, Connect CM=0.75V, LDOin = 3.3V	to LDOin LDOin			V
	Micbias Mode 0, Connect to AVdd or	LDOin	1.04		V
	Micbias Mode 1, Connect to AVdd or LDOin	1.425			V
	Micbias Mode 2, Connect to LDOin	2.075			V
	Micbias Mode 3, Connect to AVdd	AVdd			V
	Micbias Mode 3, Connect to LDOin	LDOin			V
	Noise 20kHz Current	CM=0.9V, Micbias Mode 2, A-weighted, 20Hz to bandwidth, load = 0mA.	10		μ V RMS
	Current Sourcing	Micbias Mode 2, Connect to LDOin Micbias Mode 3, Connect to AVdd	3 140		mA
	Inline Resistance	Micbias Mode 3, Connect to LDOin	87		Ω

SLOS602A-SEPTEMBER 2008-REVISED OCTOBER 2008

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT Device Setup Full scale output voltage (0dB)	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT Load = 10 k Ω (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.9V DOSR = 128, MCLK=256* f s , Channel Gain = 0dB, word length = 16 bits, Processing Block = PRB_P1, Power Tune = PTM_P3	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT 0.5	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT V RMS
SNR	Signal-to-noise ratio A-weighted (1) (2)	All zeros fed to DAC input	87	100		dB
DR	Dynamic range, A-weighted (1) (2)	-60dB 1kHz input full-scale signal, Word length=20 bits		100		dB
THD+N	Total Harmonic Distortion plus Noise	-3dB full-scale, 1-kHz input signal		-83	-70	dB
	DAC Gain Error	0 dB, 1kHz input full scale signal		0.3		dB
	DAC Mute Attenuation	Mute		119		dB
	DAC channel separation	-1 dB, 1kHz signal, between left and right HP out 100mVpp, 1kHz signal applied to AVdd		113 73		dB dB
	DAC PSRR	100mVpp, 217Hz signal applied to AVdd		77		dB
AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT Device Setup Full scale output voltage (0dB)	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT Load = 10 k Ω (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.75V; AVdd=1.5V DOSR = 128 MCLK=256* fs Channel Gain = -2dB word length = 20-bits Processing Block = PRB_P1 Power Tune = PTM_P4	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT 0.375	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED LINE OUTPUT V RMS
SNR	Signal-to-noise ratio, A-weighted (1) (2)	All zeros fed to DAC input		99		dB
DR	Dynamic range, A-weighted (1) (2)	-60dB 1 kHz input full-scale signal		97		dB
THD+N	Total Harmonic Distortion plus Noise	-1 dB full-scale, 1-kHz input signal		-85		dB
AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT Device Setup Full scale output voltage (0dB)	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16 Ω (single-ended), 50pF Headphone Output on AVdd Supply, Input & Output CM=0.9V, DOSR = 128, MCLK=256* f s , Channel Gain=0dB word length = 16 bits; Processing Block = PRB_P1 Power Tune = PTM_P3	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT 0.5	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT V RMS
SNR	Signal-to-noise ratio, A-weighted (1) (2)	All zeros fed to DAC input	87	100		dB
DR	Dynamic range, A-weighted (1) (2)	-60dB 1kHz input full-scale signal, Word Length = 20 bits, Power Tune = PTM_P4		99		dB
THD+N	Total Harmonic Distortion plus Noise	-3dB full-scale, 1-kHz input signal		-83	-70	dB
	DAC Gain Error	0dB, 1kHz input full scale signal		-0.3		dB
	DAC Mute Attenuation	Mute		122		dB
	DAC channel separation	-1dB, 1kHz signal, between left and right HP out 100mVpp, 1kHz signal applied to AVdd		110 73		dB dB
	DAC PSRR	100mVpp, 217Hz signal applied to AVdd		78		dB

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

	PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
	Power Delivered	R L =16 Ω , Output Stage on AVdd = 1.8V THDN < 1%, Input CM=0.9V, Output CM=0.9V	15		mW
	Power Delivered	R L =16 Ω Output Stage on LDOIN = 3.3V, THDN < 1% Input CM=0.9V, Output CM=1.65V	64		mW
AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT Device Setup	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16 Ω (single-ended), 50pF, Headphone Output on AVdd Supply, Input & Output CM=0.75V; AVdd=1.5V, DOSR = 128, MCLK=256* f s , Channel Gain = -2dB, word length=20-bits; Processing Block = PRB_P1, Power Tune = PTM_P4	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT	AUDIO DAC - STEREO SINGLE-ENDED HEADPHONE OUTPUT
	Full scale output voltage (0dB)		0.375		V RMS
SNR	Signal-to-noise ratio, A-weighted (1) (2)	All zeros fed to DAC input	99		dB
DR	Dynamic range, A-weighted (1) (2)	-60dB 1 kHz input full-scale signal	98		dB
THD+N	Total Harmonic Distortion plus Noise	-1dB full-scale, 1-kHz input signal	-83		dB
AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT	AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT Device Setup	AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT Load = 32 Ω (differential), 50pF, Headphone Output on LDOIN Supply Input CM = 0.75V, Output CM=1.5V, AVdd=1.8V, LDOIN=3.0V, DOSR = 128 MCLK=256* f s , Channel (headphone driver) Gain = 5dB for full scale output signal, word length=16-bits, Processing Block = PRB_P1, Power Tune = PTM_P3	AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT	AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT	AUDIO DAC - MONO DIFFERENTIAL HEADPHONE OUTPUT
	Full scale output voltage (0dB)		1778		mV RMS
SNR	Signal-to-noise ratio, A-weighted (1) (2)	All zeros fed to DAC input	98		dB
DR	Dynamic range, A-weighted (1) (2)	-60dB 1kHz input full-scale signal	96		dB
THD	Total Harmonic Distortion	-3dB full-scale, 1-kHz input signal	-82		dB
		R L =32 Ω , Output Stage on LDOIN = 3.3V, THDN < 1%, Input CM=0.9V, Output CM=1.65V	136		mW
	Power Delivered	R L =32 Ω Output Stage on LDOIN = 3.0V, THDN < 1% Input CM=0.9V, Output CM=1.5V	114		mW
LOW DROPOUT REGULATOR (AVdd)	LOW DROPOUT REGULATOR (AVdd)	LOW DROPOUT REGULATOR (AVdd) LDOMode = 1, LDOin > 1.95V	LOW DROPOUT REGULATOR (AVdd) 1.67	LOW DROPOUT REGULATOR (AVdd)	LOW DROPOUT REGULATOR (AVdd)
	Output Voltage	LDOMode = 0, LDOin > 2.0V LDOMode = 2, LDOin > 2.05V	1.72 1.77		V
	Output Voltage Accuracy		± 2		%
	Load Regulation	Load current range 0 to 50mA	15		mV
	Line Regulation Decoupling Capacitor	Input Supply Range 1.9V to 3.6V	5		mV μ F
Bias	Current		60		μ A
LOW DROPOUT REGULATOR (DVdd)	LOW DROPOUT REGULATOR (DVdd)	LOW DROPOUT REGULATOR (DVdd)	LOW DROPOUT REGULATOR (DVdd)	LOW DROPOUT REGULATOR (DVdd)	LOW DROPOUT REGULATOR (DVdd)
		LDOMode = 1, LDOin > 1.95V	1.67		V
Output	Voltage	LDOMode = 0, LDOin > 2.0V	1.72		V
		LDOMode = 2, LDOin > 2.05V	1.77		V
	Output Voltage Accuracy Load Regulation		± 2		%
		Load current range 0 to 50mA Input Supply Range 1.9V to 3.6V	15		mV
Decoupling	Line Regulation Capacitor		5		mV μ F
	Bias Current		60		μ A

SLOS602A-SEPTEMBER 2008-REVISED OCTOBER 2008

At 25 ° C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μ F on REF PIN, PLL disabled unless otherwise noted.

PARAMETER	TEST CONDITIONS	MIN	TYP	UNIT
REFERENCE
Reference Voltage Settings	CMMode = 0 (0.9V)		0.9	V
Reference Voltage Settings	CMMode = 1 (0.75V)		0.75	V
Reference Noise	CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, C ref = 10 μ F		1	μ V RMS
Decoupling Capacitor		1	10	μ F
Bias Current			120	μ A
Shutdown Current
Device Setup	Coarse AVdd supply turned off LDO_select held at ground No external digital input is toggled.
I(DVdd)			0.9	μ A
I(AVdd)			<0.9	μ A
I(LDOin)			<0.9	μ A
I(IOVDD)			13	nA

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

		VALUE	UNIT
AVdd to AVss	AVdd to AVss	-0.3 to 2.2	V
DVdd to DVss	DVdd to DVss	-0.3 to 2.2	V
IOVDD to IOVSS	IOVDD to IOVSS	-0.3 to 3.9	V
LDOIN to AVss	LDOIN to AVss	-0.3 to 3.9	V
Digital Input voltage to ground	Digital Input voltage to ground	-0.3 to IOVDD + 0.3	V
Analog input voltage to ground	Analog input voltage to ground	-0.3 to AVdd + 0.3	V
Operating temperature range	Operating temperature range	-40 to 85	° C
Storage temperature range	Storage temperature range	-55 to 125	° C
Junction temperature (T J Max)	Junction temperature (T J Max)	105	° C
	Power dissipation (with thermal pad soldered to board)	(T J Max - TA)/ θ JA	W
	θ JA Thermal impedance	35	C/W
Lead Temperature	Infrared (15 sec)	260	° C

Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
LDOIN	Power Supply Voltage Range	Referenced to AVss (1)	1.9		3.6	V
AVdd			1.5	1.8	1.95	V
IOVDD		Referenced to IOVSS (1)	1.1		3.6	V
DVdd (2)		Referenced to DVss (1)	1.26	1.8	1.95	V
	PLL Input Frequency	Clock divider uses fractional divide (D > 0), P=1, D Vdd ≥ 1.65V (Refer to Table 5-23)	10		20	MHz
		Clock divider uses integer divide (D = 0), P=1, D Vdd ≥ 1.65V (Refer to Table 5-23)	0.512		20	MHz
MCLK	Master Clock Frequency	MCLK; Master Clock Frequency; D Vdd ≥ 1.65V MCLK; Master Clock Frequency; D Vdd ≥ 1.26V			50 25	MHz
SCL	SCL Clock Frequency				400	kHz
LOL, LOR	Stereo line output load resistance		0.6	10		k Ω
HPL, HPR	Stereo headphone output load resistance	Single-ended configuration	14.4	16		Ω
HPL, HPR	Headphone output load resistance	Differential configuration	24.4	32		Ω
C Lout	Digital output load capacitance			10		pF
TOPR	Operating Temperature Range		-40		85	° C

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
TLV320AIC3204	Texas Instruments	—
TLV320AIC3204IRHBR	Texas Instruments	32-VFQFN Exposed Pad
TLV320AIC3204IRHBT	Texas Instruments	32-VFQFN Exposed Pad

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