Overview

Part: STM32L476xx from ST

Type: Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU

Key Specs:

Power supply: 1.71 V to 3.6 V
Temperature range: -40 °C to 85/105/125 °C
Core frequency: Up to 80 MHz
Performance: 100 DMIPS
Flash memory: Up to 1 MB
SRAM: Up to 128 KB
Run mode current (LDO Mode): 100 μA/MHz
Run mode current (@3.3 V SMPS Mode): 39 μA/MHz
Wakeup from Stop mode: 4 µs

Features:

Ultra-low-power with FlexPowerControl
300 nA in V_BAT mode
30 nA Shutdown mode (5 wakeup pins)
120 nA Standby mode (5 wakeup pins)
420 nA Standby mode with RTC
1.1 µA Stop 2 mode, 1.4 µA with RTC
Batch acquisition mode (BAM)
Brown out reset (BOR)
Interconnect matrix
Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™)
MPU, DSP instructions
1.25 DMIPS/MHz (Drystone 2.1)
273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz)
294 ULPMark™ CP score
106 ULPMark™ PP score
Clock Sources: 4 to 48 MHz crystal oscillator, 32 kHz crystal oscillator for RTC, Internal 16 MHz factory-trimmed RC (±1%), Internal low-power 32 kHz RC (±5%), Internal multispeed 100 kHz to 48 MHz oscillator
3 PLLs for system clock, USB, audio, ADC
Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
RTC with HW calendar, alarms and calibration
LCD 8× 40 or 4× 44 with step-up converter
Up to 24 capacitive sensing channels
16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers, 2x watchdogs, SysTick timer
Memories: 2 banks read-while-write, proprietary code readout protection, 32 KB SRAM with hardware parity check
External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
Quad SPI memory interface
4x digital filters for sigma delta modulator
Rich analog peripherals (independent supply): 3x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 2x 12-bit DAC output channels, 2x operational amplifiers with built-in PGA,

Pin Configuration

| | | | | | | | | | Tak | ole 1 | 6. ST | M32L476x | x pir | n defini | tions | s (continued) | |--------|-------------|---------|--------------|---------|--------------|---------|----------|---------------|---------|--------------|----------|------------------------------------------|----------|---------------|-------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------| | | | | | | Pin | Num | ber | | | | | | | | | Pin function | ons | | LQFP64 | LQFP64_SMPS | WLCSP72 | WLCSP72_SMPS | WLCSP81 | WLCSP99_SMPS | LQFP100 | UFBGA132 | UFBGA132_SMPS | LQFP144 | LQFP144_SMPS | UFBGA144 | Pin name
(function
after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 33 | 33 | H1 | H1 | H1 | H3 | 51 | L12 | L12 | 73 | 73 | K10 | PB12 | I/O | FT_I | - | TIM1_BKIN, TIM1_BKIN_COMP2,
I2C2_SMBA, SPI2_NSS,
DFSDM1_DATIN1, USART3_CK,
LPUART1_RTS_DE,
TSC_G1_IO1, LCD_SEG12,
SWPMI1_IO, SAI2_FS_A,
TIM15_BKIN, EVENTOUT | - | | 34 | 34 | H2 | H2 | H2 | H2 | 52 | K12 | K12 | 74 | 74 | J9 | PB13 | I/O | FT_fl | - | TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT | - | | 35 | 35 | G2 | G3 | G2 | H1 | 53 | K11 | K11 | 75 | 75 | J10 | PB14 | I/O | FT_fl | - | TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT | - | | 36 | 36 | G1 | G1 | G1 | G2 | 54 | K10 | K10 | 76 | 76 | L12 | PB15 | I/O | FT_I | - | RTC_REFIN, TIM1_CH3N,
TIM8_CH3N, SPI2_MOSI,
DFSDM1_CKIN2, TSC_G1_IO4,
LCD_SEG15,
SWPMI1_SUSPEND,
SAI2_SD_A, TIM15_CH2,
EVENTOUT | - |

577
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Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 31 and Table 72, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Table 72. I/O AC characteristics(1)(2)

| Speed | Symbol | Parameter |-------|--------| | | | | | | | | | | | | | | | | | | 00 | Tr/Tf | | | | | | | | | | | | | | | | | | | | | | | Fmax | | | | | | | 01 | | | | | | | | | | | | | Tr/Tf | | | | | | Table 72. I/O AC characteristics(1)(2) (continued)

| Speed | Symbol | Parameter | Conditions | Min | Max | Unit | |-------|--------|------------------------------------|-------------------------------|-----|--------|------|--| | | | | C=50 pF, 2.7 V≤VDDIOx≤3.6 V | - | 50 | | | | | C=50 pF, 1.62 V≤VDDIOx≤2.7 V | - | 25 | | | Fmax | | C=50 pF, 1.08 V≤VDDIOx≤1.62 V | - | 5 | | | | Maximum frequency | C=10 pF, 2.7 V≤VDDIOx≤3.6 V | - | 100(3) | MHz | | | | | C=10 pF, 1.62 V≤VDDIOx≤2.7 V | - | 37.5 | | | | | C=10 pF, 1.08 V≤VDDIOx≤1.62 V | - | 5 | | 10 | | | C=50 pF, 2.7 V≤VDDIOx≤3.6 V | - | 5.8 | | | | | C=50 pF, 1.62 V≤VDDIOx≤2.7 V | - | 11 | | | | Tr/Tf
Output rise and fall time | C=50 pF, 1.08 V≤VDDIOx≤1.62 V | - | 28 | | | | | C=10 pF, 2.7 V≤VDDIOx≤3.6 V | - | 2.5 | ns | | | | | C=10 pF, 1.62 V≤VDDIOx≤2.7 V | - | 5 | | | | | C=10 pF, 1.08 V≤VDDIOx≤1.62 V | - | 12 | | | | | C=30 pF, 2.7 V≤VDDIOx≤3.6 V | - | 120(3) | | | | | C=30 pF, 1.62 V≤VDDIOx≤2.7 V | - | 50 | | | | | C=30 pF, 1.08 V≤VDDIOx≤1.62 V | - | 10 | | | Fmax | Maximum frequency | C=10 pF, 2.7 V≤VDDIOx≤3.6 V | - | 180(3) | MHz | | 11 | | | C=10 pF, 1.62 V≤VDDIOx≤2.7 V | - | 75 | | | | | C=10 pF, 1.08 V≤VDDIOx≤1.62 V | - | 10 | | | | | C=30 pF, 2.7 V≤VDDIOx≤3.6 V | - | 3.3 | | | Tr/Tf | Output rise and fall time | C=30 pF, 1.62 V≤VDDIOx≤2.7 V | - | 6 | ns | | | | | C=30 pF, 1.08 V≤VDDIOx≤1.62 V | - | 16 | | | Fmax | Maximum frequency | | - | 1 | MHz | | Fm+ | Tf | Output fall time(4) | C=50 pF, 1.6 V≤VDDIOx≤3.6 V | - | 5 | ns | ^1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0351 reference manual for a description of GPIO Port configuration register.

^2. Guaranteed by design.

^3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

^4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

Figure 31. I/O AC characteristics definition(1)

1. Refer to Table 72: I/O AC characteristics.

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 20. Voltage characteristics(1)

Symbol	Ratings		Min	Max	Unit
VDDX - VSS	External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT, VREF+)		-0.3	4.0	V
	External SMPS supply voltage	Range 1	-0.3	1.4	V
VDD12 - VSS		Range 2	-0.3
Symbol	Ratings	Min	Max	Unit
--------------	--------------------------------------------------------------------	---------	------------------------------------------------------	------
	Input voltage on FT_xxx pins	VSS-0.3	min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) + 4.0(3)(4)
VIN(2)	Input voltage on TT_xx pins	VSS-0.3	4.0	V
	Input voltage on BOOT0 pin	VSS	9.0
	Input voltage on any other pins	VSS-0.3	4.0
∆VDDx	Variations between different VDDX power pins of the same domain	-	50	mV
VSSx-VSS	Variations between all the different ground pins(5)	-	50	mV
VREF+ - VDDA	Allowed voltage difference for VREF+ > VDDA	-	0.4	V

Table 20. Voltage characteristics(1) (continued)

1. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
1. Include VREF- pin.

Table 21. Current characteristics

Symbol	Ratings	Max	Unit
∑IVDD	power lines (source)(1)(2) Total current into sum of all VDD	150
∑IVSS	ground lines (sink)(1) Total current out of sum of all VSS	150
IVDD(PIN)	power pin (source)(1)(2) Maximum current into each VDD	100
IVSS(PIN)	ground pin (sink)(1) Maximum current out of each VSS	100
	Output current sunk by any I/O and control pin except FT_f	20
IIO(PIN)	Output current sunk by any FT_f pin	20
	Output current sourced by any I/O and control pin	20	mA
	Total output current sunk by sum of all I/Os and control pins(3)	100
∑IIO(PIN)	Total output current sourced by sum of all I/Os and control pins(3)	100
IINJ(PIN)(4)	Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5	-5/+0(5)
	Injected current on PA4, PA5	-5/0
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(6)	25
^1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range.

^4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

^1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum must always be respected. Refer to Table 21: Current characteristics for the maximum allowed injected current values.

^2. Valid also for VDD12 on SMPS packages.

^3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the minimum allowed input voltage values.
When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions.

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

$$T_J \max = T_A \max + (P_D \max x \Theta_{JA})$$

Where:

TA max is the maximum ambient temperature in °C,
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$$P_{I/O}$$ max = $\Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DDIOx} - V_{OH}) \times I_{OH})$ ,

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol	Parameter	Value	Unit
	Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch	45
	Thermal resistance junction-ambient LQFP100 - 14 × 14mm	42
	Thermal resistance junction-ambient LQFP144 - 20 × 20 mm	32
	Thermal resistance junction-ambient UFBGA144 - 10 × 10 mm	53
ΘJA	Thermal resistance junction-ambient UFBGA132 - 7 × 7 mm	55	°C/W
	Thermal resistance junction-ambient WLCSP72	46
	Thermal resistance junction-ambient WLCSP81	41
	Thermal resistance junction-ambient WLCSP99	42
Table 133. Package thermal characteristics

7.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org

STM32L476xx Package information

7.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32L476xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature $T_{Amax}$ = 82 °C (measured according to JESD51-2), $I_{DDmax}$ = 50 mA, $V_{DD}$ = 3.5 V, maximum 20 I/Os used at the same time in output at low level with $I_{OL}$ = 8 mA, $V_{OL}$ = 0.4 V and maximum 8 I/Os used at the same time in output at low level with $I_{OL}$ = 20 mA, $V_{OL}$ = 1.3 V

P_{INTmax} = 50 \text{ mA} \times 3.5 \text{ V} = 175 \text{ mW}

$P_{IOmax} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} + 8 \times 20 \text{ mA} \times 1.3 \text{ V} = 272 \text{ mW}$

This gives: P_INTmax = 175 mW and P_IOmax = 272 mW:

$$P_{Dmax} = 175 + 272 = 447 \text{ mW}$$

Using the values obtained in Table 133 T_Jmax is calculated as follows:

    For LQFP64, 45 °C/W

T_{\text{Imax}} = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C

This is within the range of the suffix 6 version parts ( $-40 < T_J < 105$ °C) see Section 8: Ordering information.

In this case, parts must be ordered at least with the temperature range suffix 6 (see Part numbering).

Note:

With this given $P_{Dmax}$ user can find the $T_{Amax}$ allowed for a given device temperature range (order code suffix 6 or 7).

Suffix 6: T_{Amax} = T_{Jmax} - (45^{\circ}\text{C/W} \times 447 \text{ mW}) = 105\text{-}20.115 = 84.885 ^{\circ}\text{C}
Suffix 7: T_{Amax} = T_{Jmax} - (45^{\circ}\text{C/W} \times 447 \text{ mW}) = 125\text{-}20.115 = 104.885 ^{\circ}\text{C}

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature $T_J$ remains within the specified range.

4

DS10198 Rev 11 259/270

Assuming the following application conditions:

Maximum ambient temperature $T_{Amax}$ = 100 °C (measured according to JESD51-2), $I_{DDmax}$ = 20 mA, $V_{DD}$ = 3.5 V, maximum 20 I/Os used at the same time in output at low level with $I_{OL}$ = 8 mA, $V_{OL}$ = 0.4 V

$P_{INTmax}$ = 20 mA × 3.5 V = 70 mW

$P_{IOmax} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} = 64 \text{ mW}$

This gives: $P_{INTmax} = 70 \text{ mW}$ and $P_{IOmax} = 64 \text{ mW}$ :

$P_{Dmax} = 70 + 64 = 134 \text{ mW}$

Thus: P_Dmax = 134 mW

Using the values obtained in Table 133 T_Jmax is calculated as follows:

For LQFP64, 45 °C/W

$$T_{Jmax}$$ = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C

This is above the range of the suffix 6 version parts ( $-40 < T_J < 105$ °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

Refer to Figure 77 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements.

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STM32L476RGT6