STM32L476VXT

Part: STM32L476RGT6 (STM32L476xx family) — STMicroelectronics

Type: Ultra-low-power ARM Cortex-M4 32-bit MCU with FPU

Description: Ultra-low-power 32-bit Arm Cortex-M4 MCU with FPU at up to 80 MHz (100 DMIPS), up to 1 MB flash and 128 KB SRAM, 1.71–3.6 V supply, with USB OTG FS, LCD controller and external SMPS support.

Operating Conditions:

• Supply voltage (VDD): 1.71–3.6 V
• Operating temperature: -40 to 85 °C for suffix 6 at maximum power dissipation (suffix 6 reaches 105 °C only in low-power dissipation; suffix 7 is -40 to 105 °C, suffix 3 is -40 to 125 °C)
• Max CPU/AHB/APB clock: 80 MHz
• Junction temperature (suffix 6): -40 to 105 °C

Absolute Maximum Ratings:

• Max external main supply voltage (VDDX - VSS): 4.0 V
• Max total current into all VDD lines: 150 mA
• Max current into each VDD pin: 100 mA
• Max output current sunk or sourced by any I/O pin: 20 mA
• Max junction temperature: 150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• VDD: 1.71–3.6 V; VDDA: 1.62–3.6 V when ADC or COMP is used
• VBAT backup voltage: 1.55–3.6 V
• Core clock: up to 80 MHz, 1.25 DMIPS/MHz
• Power dissipation (LQFP64, TA = 85 °C, suffix 6): 444 mW max
• Run mode: 100 μA/MHz (LDO) and 39 μA/MHz (SMPS at 3.3 V)
• Low-power modes: Shutdown 30 nA, Standby 120 nA, Stop 2 1.1 μA, VBAT mode 300 nA
• Wakeup from Stop mode: 4 μs
• Input voltage on BOOT0: up to 9.0 V (abs max)

Features:

• Arm Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator for 0-wait-state flash execution
• Up to 1 MB flash (2 banks, read-while-write) and up to 128 KB SRAM (32 KB with hardware parity)
• 3x 12-bit ADC at 5 Msps, 2x 12-bit DAC, 2x op-amps, 2x comparators
• USB OTG FS, CAN 2.0B, SDMMC, 3x I2C, 5x USART, 1x LPUART, 3x SPI, Quad SPI, 2x SAI
• LCD controller (8x40 or 4x44), up to 24 touch-sensing channels
• 16 timers, 14-channel DMA, RNG, CRC unit, 96-bit unique ID
• External memory interface (FSMC) for SRAM, PSRAM, NOR and NAND
• SWD, JTAG and Embedded Trace Macrocell debug
• Internal multispeed 100 kHz–48 MHz oscillator and 3 PLLs
• ECOPACK2 compliant

Applications:

Package:

• LQFP64 (STM32L476RG)
• Other family packages: LQFP144, LQFP100, UFBGA144, UFBGA132, WLCSP99, WLCSP81, WLCSP72

Figure 6. STM32L476Zx LQFP144 pinout (1)(2)

1. The above figure shows the package top view.
2. The I/O pins supplied by V DDIO2 are shown in gray.

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Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout (1)(2)

1. The above figure shows the package top view.
2. The I/O pins supplied by V DDIO2 are shown in gray.

The definition and values of input/output AC characteristics are given in Figure 31 and Table 72 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions .

Table 72. I/O AC characteristics (1)(2)

Table 72. I/O AC characteristics (1)(2)

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Table 72. I/O AC characteristics (1)(2) (continued)

1. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
2. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

Figure 31. I/O AC characteristics definition (1)

1. Refer to Table 72: I/O AC characteristics .

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics , Table 21: Current characteristics and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 20. Voltage characteristics (1)

Table 20. Voltage characteristics (1)

Table 20. Voltage characteristics (1) (continued)

1. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. Include VREF- pin.

Table 21. Current characteristics

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1. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the minimum allowed input voltage values.
2. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.