STM32G431CBU6

Part: STM32G431x6/x8/xB from STMicroelectronics

Type: Arm® Cortex®-M4 32-bit MCU+FPU

Key Specs:

• Core Frequency: 170 MHz
• DMIPS: 213 DMIPS
• Flash Memory: up to 128 KB
• SRAM: 32 KB
• Operating Voltage: 1.71 V to 3.6 V
• ADC Conversion Time: 0.25 µs
• ADC Resolution: up to 16-bit
• DAC Buffered External Channels Speed: 1 MSPS
• DAC Unbuffered Internal Channels Speed: 15 MSPS

Features:

• Arm® 32-bit Cortex®-M4 CPU

Includes ST state-of-the-art patented technology

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions
• Operating conditions:
  • VDD, VDDA voltage range: 1.71 V to 3.6 V
• Mathematical hardware accelerators
  • CORDIC for trigonometric functions acceleration
  • FMAC: filter mathematical accelerator
• Memories
  • 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP
  • 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes
  • Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)
• Reset and supply management
  • Power-on/power-down reset (POR/PDR/BOR)
  • Programmable voltage detector (PVD)
  • Low-power modes: sleep, stop, standby and shutdown
  • VBAT supply for RTC and backup registers

• Clock management

  • 4 to 48 MHz crystal oscillator
  • 32 kHz oscillator with calibration
  • Internal 16 MHz RC with PLL option (± 1%)
  • Internal 32 kHz RC oscillator (± 5%)

• Up to 86 fast I/Os

  • All mappable on external interrupt vectors
  • Several I/Os with 5 V tolerant capability

• Interconnect matrix

• 12-channel DMA controller

• 2 x ADCs 0.25 µs (up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range

• 4 x 12-bit DAC channels

  • 2 x buffered external channels 1 MSPS
  • 2 x unbuffered internal channels 15 MSPS

• 4 x ultra-fast rail-to-rail analog comparators

• 3 x operational amplifiers that can be used in PGA mode, all terminals accessible

• Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.9 V)

• 14 timers:

  • 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop

• 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop

• 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop

• 2 x watchdog timers (independent, window)

• 1 x SysTick timer: 24-bit downcounter

• 2 x 16-bit basic timers

• 1 x low-power timer

• Calendar RTC with alarm, periodic wakeup from stop/standby

• Communication interfaces

  • 1 x FDCAN controller supporting flexible data rate
  • 3 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop

• 4 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)

• 1 x LPUART

• 3 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface

• 1 x SAI (serial audio interface)

• USB 2.0 full-speed interface with LPM and BCD support

• IRTIM (infrared interface)

• USB Type-C™ /USB power delivery controller (UCPD)

• True random number generator (RNG)

• CRC calculation unit, 96-bit unique ID

• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

Table 1. Device summary

| Reference | Part number | |-------------|-----------------------------------------------------------------|--|--|--|--|--|--|--|--|--| | STM32G431x6 | STM32G431C6, STM32G431K6, STM32G431R6, STM32G431V6, STM32G431M6 | | STM32G431x8 | STM32G431C8, STM32G431K8, STM32G431R8, STM32G431V8, STM32G431M8 | | STM32G431xB | STM32G431CB, STM32G431KB, STM32G431RB, STM32G431VB, STM32G431MB |

The definition and values of input/output AC characteristics are given in Figure 26 and Table 55, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions.

^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Guaranteed by design.

Table 55. I/O (except FT_c) AC characteristics(1) (2)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			C=50 pF, 2.7 V≤VDD≤3.6 V	-	5
		Maximum	C=50 pF, 1.62 V≤VDD≤2.7 V	-	1
	Fmax	frequency	C=10 pF, 2.7 V≤VDD≤3.6 V	-	10	MHz
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	1.5
00			C=50 pF, 2.7 V≤VDD≤3.6 V	-	25
	Tr/Tf	Output rise and	C=50 pF, 1.62 V≤VDD≤2.7 V	-	52
		fall time	C=10 pF, 2.7 V≤VDD≤3.6 V	-	17	ns
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	37
	Fmax		C=50 pF, 2.7 V≤VDD≤3.6 V	-	25
		Maximum frequency	C=50 pF, 1.62 V≤VDD≤2.7 V	-	10
			C=10 pF, 2.7 V≤VDD≤3.6 V	-	50	MHz
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	15
01		Output rise and fall time	C=50 pF, 2.7 V≤VDD≤3.6 V	-	9
			C=50 pF, 1.62 V≤VDD≤2.7 V	-	16
	Tr/Tf		C=10 pF, 2.7 V≤VDD≤3.6 V	-	4.5	ns
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	9
	Fmax	Maximum frequency	C=50 pF, 2.7 V≤VDD≤3.6 V	-	50	MHz
			C=50 pF, 1.62 V≤VDD≤2.7 V	-	25
			C=10 pF, 2.7 V≤VDD≤3.6 V	-	100(3)
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	37.5
10			C=50 pF, 2.7 V≤VDD≤3.6 V	-	5.8
		Output rise and	C=50 pF, 1.62 V≤VDD≤2.7 V	-	11
	Tr/Tf	fall time	C=10 pF, 2.7 V≤VDD≤3.6 V	-	2.5	ns
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	5
			C=30 pF, 2.7 V≤VDD≤3.6 V	-	120(3)
		Maximum	C=30 pF, 1.62 V≤VDD≤2.7 V	-	50
	Fmax	frequency	C=10 pF, 2.7 V≤VDD≤3.6 V	-	180(3)	MHz
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	75
11			C=30 pF, 2.7 V≤VDD≤3.6 V	-	3.3
		Output rise and	C=30 pF, 1.62 V≤VDD≤2.7 V	-	6
	Tr/Tf	fall time(4)	C=10 pF, 2.7 V≤VDD≤3.6 V	-	1.7	ns
			C=10 pF, 1.62 V≤VDD≤2.7 V	-	3.3
Table 55. I/O (except FT_c) AC characteristics(1) (2) (continued)
-------------------------------------------------------------------	--	--	--	--
-------------------------------------------------------------------	--	--	--	--

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
FM+	Fmax(5)	Maximum frequency		-	1	MHz
	Tr/TF(4)	Output high to low level fall time	C=50 pF, 1.6 V≤VDD≤3.6 V	-	5	ns

• 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®- based 32-bit MCUs" for a description of GPIO Port configuration register.
• 1. Guaranteed by design.
• 1. This value represented the I/O capability but maximum system frequency is 170 MHz.
• 4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
• 1. The maximum frequency is defined with the following conditions:
  • (Tr+ Tf) ≤ 2/3 T.
  • 45%<Duty cycle<55%

Table 56. I/O FT_c AC characteristics(1) (2)

| Speed | Symbol | Parameter | Conditions | Min | Max | Unit | |-------|--------|---------------------------------|--------------------------|--------------------------|-----|------|--| | | | Maximum
Fmax
frequency | C=50 pF, 2.7 V≤VDD≤3.6 V | - | 2 | | | | | C=50 pF, 1.6 V≤VDD≤2.7 V | - | 1 | MHz | | 0 | Tr/Tf | Output H/L to | | C=50 pF, 2.7 V≤VDD≤3.6 V | - | 170 | | | | L/H level fall
time | C=50 pF, 1.6 V≤VDD≤2.7 V | - | 330 | ns | | | | Maximum
Fmax
frequency | C=50 pF, 2.7 V≤VDD≤3.6 V | - | 10 | | | | | C=50 pF, 1.6 V≤VDD≤2.7 V | - | 5 | MHz | | 1 | | Output H/L to | C=50 pF, 2.7 V≤VDD≤3.6 V | - | 35 | | | | Tr/Tf
L/H level fall
time | C=50 pF, 1.6 V≤VDD≤2.7 V | - | 65 | ns |

• 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm® based 32-bit MCUs" for a description of GPIO Port configuration register.
• 1. Guaranteed by design.

Figure 26. I/O AC characteristics definition⁽¹⁾

1. Refer to Table 55: I/O (except FT_c) AC characteristics.

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol Ratings Min Max Unit VDD - VSS External main supply voltage (including VDD, VDDA, VBAT and VREF+) -0.3 4.0 V VIN(2) Input voltage on FT_xxx pins except FT_c pins VSS-0.3 min (VDD, VDDA) + 4.0(3)(4) Input voltage on FT_c pins VSS-0.3 5.5 Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on any other pins VSS-0.3 4.0 ^|∆VDDx| Variations between different VDDX power pins of the same domain - 50 mV |VSSx-VSS| Variations between all the different ground pins(5) - 50 VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V

Table 14. Voltage characteristics(1)

^1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

• 1. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum allowed injected current values.
• 1. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
• 1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
• 1. Include VREF- pin.

Table 15. Current characteristics

Symbol	Ratings	Max	Unit
∑IVDD	power lines (source)(1) Total current into sum of all VDD	150
∑IVSS	ground lines (sink)(1) Total current out of sum of all VSS	150
IVDD(PIN)	power pin (source)(1) Maximum current into each VDD	100
IVSS(PIN)	ground pin (sink)(1) Maximum current out of each VSS	100
	Output current sunk by any I/O and control pin except FT_f	20
IIO(PIN)	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	20
	Total output current sunk by sum of all I/Os and control pins(2)	100
∑IIO(PIN)	Total output current sourced by sum of all I/Os and control pins(2)	100
IINJ(PIN)(3)	Injected current on FT_xxx, TT_xx, NRST pins	-5/0(4)
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	±25

• 1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range.
• 1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
• 1. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
• 1. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14: Voltage characteristics for the minimum allowed input voltage values.
• 1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 16. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$$P_{I/O}$$ max = $\Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DDIOx} - V_{OH}) \times I_{OH})$ ,

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 100. Package thermal characteristics

Symbol	Parameter	Value	Unit
	Thermal resistance junction-ambient LQFP100 - 14 × 14 mm	48.9
	Thermal resistance junction-ambient LQFP80 - 12 × 12 mm	49.7
	Thermal resistance junction-ambient LQFP64 - 10 × 10 mm	50.8
	Thermal resistance junction-ambient LQFP48 - 7 × 7 mm	58.4 58.4	°C/W
ΘJA	Thermal resistance junction-ambient LQFP32 - 7 × 7 mm
	Thermal resistance junction-ambient UFBGA64 - 5 × 5 mm	44.2
	Thermal resistance junction-ambient UFQFPN48 - 7 × 7 mm	28.6
	Thermal resistance junction-ambient UFQFPN32 - 5 × 5 mm	36.7
	Thermal resistance junction-ambient WLCSP49 - pitch 0.4	59
Table 100. Package thermal characteristics (continued)

Symbol	Parameter	Value	Unit
ΘJC	Thermal resistance junction-case LQFP100 - 14 × 14 mm	10.3
	Thermal resistance junction-case LQFP80 - 12 × 12 mm	10.3
	Thermal resistance junction-case LQFP64 - 10 × 10 mm	10.1
	Thermal resistance junction-case LQFP48 - 7 × 7 mm	11.9
	Thermal resistance junction-case LQFP32 - 7 × 7 mm	11.9	°C/W
	Thermal resistance junction-case UFBGA64 - 5 × 5 mm	14.78
	Thermal resistance junction-case UFQFPN48 - 7 × 7 mm	3.1(1) 9.4
	Thermal resistance junction-case UFQFPN32 - 5 × 5 mm	3.4(1) 14.2
	Thermal resistance junction-case WLCSP49 - pitch 0.4	2.33
	Thermal resistance junction-board LQFP100 - 14 × 14 mm	25.7
ΘJB	Thermal resistance junction-board LQFP80 - 12 × 12 mm	25.1
	Thermal resistance junction-board LQFP64 - 10 × 10 mm	24.7
	Thermal resistance junction-board LQFP48 - 7 × 7 mm	27.7
	Thermal resistance junction-board LQFP32 - 7 × 7 mm	27.7	°C/W
	Thermal resistance junction-board UFBGA64 - 5 × 5 mm	22.5
	Thermal resistance junction-board UFQFPN48 - 7 × 7 mm	15.7
	Thermal resistance junction-board UFQFPN32 - 5 × 5 mm	18.6
	Thermal resistance junction-board WLCSP49 - pitch 0.4	38.12
1. Thermal resistance junction-case where the case is the bottom thermal pad on the UFQFPN package.

6.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org

6.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 7: Ordering information.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32G431xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature $T_{Amax}$ = 82 °C (measured according to JESD51-2), $I_{DDmax}$ = 50 mA, $V_{DD}$ = 3.5 V, maximum 20 I/Os used at the same time in output at low level with $I_{OL}$ = 8 mA, $V_{OL}$ = 0.4 V and maximum 8 I/Os used at the same time in output at low level with $I_{OL}$ = 20 mA, $V_{OL}$ = 1.3 V

P_{INTmax} = 50 \text{ mA} \times 3.5 \text{ V} = 175 \text{ mW}

$P_{IOmax} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} + 8 \times 20 \text{ mA} \times 1.3 \text{ V} = 272 \text{ mW}$

This gives: P_INTmax = 175 mW and P_IOmax = 272 mW:

$$P_{Dmax} = 175 + 272 = 447 \text{ mW}$$

Using the values obtained in T_Jmax is calculated as follows:

    For LQFP100, 42 °C/W

T_{\text{lmax}} = 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C

This is within the range of the suffix 6 version parts ( $-40 < T_J < 105$ °C) see Section 7: Ordering information.

In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 7: Ordering information).

Note:

With this given $P_{Dmax}$ we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7).

Suffix 6: T_{Amax} = T_{Jmax} - (42 °C/W \times 447 ~mW) = 105-18.774 = 86.226 °C
Suffix 3: T_{Amax} = T_{Jmax} - (42 °C/W \times 447 ~mW) = 130-18.774 = 111.226 °C