STM32F746NE

Part: STM32F745xx STM32F746xx

Type: ARM Cortex-M7 32-bit MCU with FPU

Description: ARM Cortex-M7 32-bit MCU with FPU, up to 216 MHz, 462 DMIPS, up to 1MB Flash, 320+16+4KB RAM, USB OTG HS/FS, Ethernet, 18 Timers, 3 ADCs, 25 communication interfaces, camera and LCD support.

Operating Conditions:

• Supply voltage: 1.7 V to 3.6 V
• Max CPU frequency: 216 MHz

Key Specs:

• CPU Core: ARM 32-bit Cortex-M7 with FPU
• Max CPU Frequency: 216 MHz
• Performance: 462 DMIPS / 2.14 DMIPS/MHz
• Flash Memory: Up to 1MB
• SRAM: 320KB (data TCM) + 16KB (instruction TCM) + 4KB (backup)
• ADCs: 3x 12-bit, 2.4 MSPS (up to 7.2 MSPS in triple interleaved mode)
• DACs: 2x 12-bit
• I/O Ports: Up to 168, up to 166 5 V-tolerant

Features:

• ART Accelerator™ and L1-cache (4KB data, 4KB instruction)
• Memory Protection Unit (MPU) and DSP instructions
• 1024 bytes of OTP memory
• Flexible external memory controller (SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND)
• Dual mode Quad SPI
• LCD-TFT controller up to XGA resolution with Chrom-ART Accelerator™ (DMA2D)
• General-purpose DMA: 16-stream controller with FIFOs and burst support
• Debug mode: Cortex-M7 Trace Macrocell™, SWD & JTAG interfaces
• Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816, LIN, IrDA, modem control)
• Up to 4× I2C interfaces (SMBus/PMBus)
• Up to 6 SPIs (up to 50 Mbits/s), 3 with muxed simplex I2S
• 2 × CANs (2.0B active) and SDMMC interface
• 2 x SAIs (serial audio interface) and SPDIFRX interface
• USB 2.0 full-speed device/host/OTG controller with on-chip PHY
• 10/100 Ethernet MAC with dedicated DMA (IEEE 1588v2 hardware, MII/RMII)
• USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• CRC calculation unit and True random number generator
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
• Up to 18 timers (thirteen 16-bit, two 32-bit), 2x watchdogs, SysTick timer

Package:

• UFBGA176 (10x10 mm)
• TFBGA216 (13x13 mm)
• WLCSP143 (4.5x5.8 mm)
• LQFP100 (14x14 mm)
• LQFP144 (20x20 mm)
• LQFP1

• Core: ARM ® 32-bit Cortex ® -M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
• -Up to 1MB of Flash memory
• Memories
• -1024 bytes of OTP memory
• -Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
• -SRAM: 320KB (including 64KB of data TCM RAM for critical real time data) + 16KB of instruction TCM RAM (for critical real time routines) + 4KB of backup SRAM (available in the lowest power modes)
• Dual mode Quad SPI
• LCD-TFT controller up to XGA resolution with dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D)
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• -POR, PDR, PVD and BOR
• -1.7 V to 3.6 V application supply and I/Os
• -Dedicated USB power
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -4-to-26 MHz crystal oscillator
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low-power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC, 32×32 bit backup registers + 4KB backup SRAM
• 2×12-bit D/A converters
• 96-bit unique ID
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer

Figure 11. STM32F74xVx LQFP100 pinout

1. The above figure shows the package top view.

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Figure 12. STM32F74xZx WLCSP143 ballout

The above figure shows the package bump view.

Figure 13. STM32F74xZx LQFP144 pinout

1. The above figure shows the package top view.

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Figure 14. STM32F74xIx LQFP176 pinout

1. The above figure shows the package top view.

Figure 15. STM32F74xBx LQFP208 pinout

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Figure 16. STM32F74xIx UFBGA176 ballout

1. The above figure shows the package top view.

Figure 17. STM32F74xNx TFBGA216 ballout

1. The above figure shows the package top view.

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Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F745xx and STM32F746xx pin and ball definition

Table 10. STM32F745xx and STM32F746xx pin and ball definition

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1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

• The speed should not exceed 2 MHz with a maximum load of 30 pF.
• These I/Os must not be used as a current source (e.g. to drive an LED).

1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F75xxx and STM32F74xxx reference manual.
2. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
3. If the device is delivered in an WLCSP143, UFBGA176, LQFP176 or TFBGA216 package, and the BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).

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Table 11. FMC pin definition

Table 11. FMC pin definition

Table 11. FMC pin definition (continued)

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Table 11. FMC pin definition (continued)

Table 11. FMC pin definition (continued)

Unless otherwise specified, the parameters given in Table 63 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 18 .

Table 63. ADC characteristics

Table 63. ADC characteristics

Table 63. ADC characteristics (continued)

Table 63. ADC characteristics (continued)

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Table 63. ADC characteristics (continued)

1. Based on characterization, not tested in production.
2. VREF+ is internally connected to V DDA and V REFis internally connected to V SSA .
3. RADC maximum value is given for V DD =1.7 V, and minimum value for V DD =3.3 V.
4. For external triggers, a delay of 1/f PCLK2 must be added to the latency specified in Table 63 .

Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics , Table 16: Current characteristics , and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 15. Voltage characteristics

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Table 16. Current characteristics

1. A positive injection is induced by V IN >VDDA while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 15: Voltage characteristics for the values of the maximum allowed input voltage.

2. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 17. Thermal characteristics

Table 17. Thermal characteristics

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.