PIC32MX170F256B

Part: Microchip PIC32MX1XX/2XX Family Type: 32-bit Microcontroller Description: 32-bit MIPS32® M4K® microcontroller operating at up to 50 MHz with up to 256 KB Flash, 64 KB SRAM, advanced analog features including 10-bit 1.1 Msps ADC, and comprehensive communication interfaces including USB 2.0 Full-speed OTG.

Operating Conditions:

• Supply voltage: 2.3V to 3.6V
• Operating temperature: -40°C to +105°C
• Max clock frequency: 50 MHz

Absolute Maximum Ratings:

Key Specs:

• Core: 50 MHz/83 DMIPS MIPS32® M4K®
• Program Memory: Up to 256 KB Flash (plus 3 KB boot Flash)
• Data Memory: Up to 64 KB SRAM
• ADC: 10-bit, 1.1 Msps rate with one S&H, up to 13 analog inputs
• Comparators: Up to three Analog Comparator modules
• USB: USB 2.0-compliant Full-speed OTG controller
• UART: Two modules, 12.5 Mbps
• SPI: Two 4-wire modules, 25 Mbps
• I2C: Two modules, up to 1 Mbaud
• Dynamic current: 0.5 mA/MHz (typical)
• IPD current: 20 μA (typical)

Features:

• MIPS16e® mode for up to 40% smaller code size
• 0.9% internal oscillator, programmable PLLs
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
• Audio Interface with I2S, LJ, RJ, DSP modes, SPI, I2C control
• Charge Time Measurement Unit (CTMU) for mTouch™ sensing and temperature measurement
• Five General Purpose Timers (16-bit and 32-bit)
• Five Output Compare (OC) modules, Five Input Capture (IC) modules
• Real-Time Clock and Calendar (RTCC) module
• Four channels of hardware DMA (plus two for USB)
• 10 mA source/sink on all I/O pins, 5V-tolerant pins
• AEC-Q100 REVG (Grade 2) planned

Applications:

Package:

• SOIC (28-pin)
• SSOP (28-pin)
• SPDIP (28-pin)
• QFN (28-pin, 44-pin)
• VTLA (36-pin, 44-pin)
• TQFP (44-pin)

• Data communication: I2S, LJ, RJ, and DSP modes
• Control interface: SPI and I2C™
• Master clock:
  • Generation of fractional clock frequencies
  • Can be synchronized with USB clock
  • Can be tuned in run-time

This section provides an overview of the PIC32MX1XX/2XX electrical characteristics for devices that operate at 40 MHz. Refer to Section 30.0 "50 MHz Electrical Characteristics" for additional specifications for operations at higher frequency. Additional information will be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC32MX1XX/2XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.

(See Note 1)

• Storage temperature65°C to +150°C

• Voltage on VDD with respect to VSS0.3V to +4.0V

• Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)0.3V to (VDD + 0.3V)

• Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3)0.3V to +5.5V

• Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)0.3V to +3.6V

• Voltage on D+ or D- pin with respect to VUSB3V30.3V to (VUSB3V3 + 0.3V)

• Voltage on VBUS with respect to VSS0.3V to +5.5V

• Maximum current out of VSS pin(s)300 mA

• Maximum current into VDD pin(s) (Note 2)300 mA

• Maximum output current sunk by any I/O pin15 mA

• Maximum output current sourced by any I/O pin15 mA

• Maximum current sunk by all ports200 mA

• Maximum current sourced by all ports (Note 2)200 mA

• Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

  • 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2).
  • 3: See the "Pin Diagrams" section for the 5V tolerant pins.

TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

^2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 29-10 for BOR values.

TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
• 2: Data in the "Typical" column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
• 3: This parameter is characterized, but not tested in manufacturing.
• 4: IIDLE electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
• 2: Data in the "Typical" column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
• 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
• 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
• 5: IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Examples of typical application connections are shown in Figure 2-5 and Figure 2-6.

FIGURE 2-5: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION

FIGURE 2-6: AUDIO PLAYBACK APPLICATION