PIC32MX270F256D

Part: PIC32MX1XX/2XX by Microchip Type: 32-bit Microcontrollers

Key Specs:

• Operating Voltage: 2.3V to 3.6V
• Operating Temperature: -40°C to +105°C (Grade 2)
• Max CPU Frequency: 50 MHz
• CPU Core: MIPS32® M4K®
• DMIPS: 83 DMIPS
• Flash Memory: up to 256 KB
• SRAM: up to 64 KB
• ADC Resolution: 10-bit
• ADC Sample Rate: 1.1 Msps
• Dynamic Current: 0.5 mA/MHz (typical)
• IPD Current: 20 μA (typical)

Features:

• MIPS16e® mode for up to 40% smaller code size
• 0.9% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
• Audio Interface with I2S, LJ, RJ, and DSP modes
• Up to 13 analog inputs
• Charge Time Measurement Unit (CTMU) for mTouch™ capacitive touch sensing and on-chip temperature measurement
• Up to three Analog Comparator modules
• Five General Purpose Timers (16-bit and up to two 32-bit)
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS)
• Real-Time Clock and Calendar (RTCC) module
• USB 2.0-compliant Full-speed OTG controller
• Two UART modules (12.5 Mbps) with LIN 2.0 and IrDA® support
• Two 4-wire SPI modules (25 Mbps)
• Two I2C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Four channels of hardware DMA with automatic

• Data communication: I2S, LJ, RJ, and DSP modes
• Control interface: SPI and I2C™
• Master clock:
  • Generation of fractional clock frequencies
  • Can be synchronized with USB clock
  • Can be tuned in run-time

This section provides an overview of the PIC32MX1XX/2XX electrical characteristics for devices that operate at 40 MHz. Refer to Section 30.0 "50 MHz Electrical Characteristics" for additional specifications for operations at higher frequency. Additional information will be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC32MX1XX/2XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.

Absolute Maximum Ratings

(See Note 1)

• Storage temperature -65°C to +150°C
• Voltage on VDD with respect to VSS -0.3V to +4.0V
• Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) -0.3V to (VDD + 0.3V)
• Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3) -0.3V to +5.5V
• Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) -0.3V to +3.6V
• Voltage on D+ or D- pin with respect to VUSB3V3 -0.3V to (VUSB3V3 + 0.3V)
• Voltage on VBUS with respect to VSS -0.3V to +5.5V
• Maximum current out of VSS pin(s) 300 mA
• Maximum current into VDD pin(s) (Note 2)300 mA
• Maximum output current sunk by any I/O pin15 mA
• Maximum output current sourced by any I/O pin 15 mA
• Maximum current sunk by all ports 200 mA
• Maximum current sourced by all ports (Note 2)200 mA

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2).

3: See the "Pin Diagrams" section for the 5V tolerant pins.

29.1 DC Characteristics

TABLE 29-1: OPERATING MIPS VS. VOLTAGE

TABLE 29-2: THERMAL OPERATING CONDITIONS

TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 29-10 for BOR values.

TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

• 2: The test conditions for IDD measurements are as follows:
  • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
  • OSC2/CLKO is configured as an I/O input pin
  • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
  • CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1
  • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
  • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
  • All I/O pins are configured as inputs and pulled to VSS
  • MCLR = VDD
  • CPU executing while(1) statement from Flash
  • RTCC and JTAG are disabled
• 3: Data in "Typical" column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested.
• 4: This parameter is characterized, but not tested in manufacturing.
• 5: IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Note 1: The test conditions for IIDLE current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
• 2: Data in the "Typical" column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
• 3: This parameter is characterized, but not tested in manufacturing.
• 4: IIDLE electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Note 1: The test conditions for IPD current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
• 2: Data in the "Typical" column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
• 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
• 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
• 5: IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Note 1: Data in "Typical" column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

• 3: Negative current is defined as current sourced by the pin.
• 4: This parameter is characterized, but not tested in manufacturing.
• 5: See the "Pin Diagrams" section for the 5V-tolerant pins.
• 6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External "input" logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device.

TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

TABLE 29-10: ELECTRICAL CHARACTERISTICS: BOR

2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.

TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY

2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority).

3: Refer to the "PIC32 Flash Programming Specification" (DS60001145) for operating conditions during programming and erase cycles.

4: This parameter depends on FRC accuracy (See Table 29-17) and FRC tuning values (See Register 8-2).

TABLE 29-12: COMPARATOR SPECIFICATIONS

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD.

2: These parameters are characterized but not tested.

3: Settling time measured while CVRR = 1 and CVR<3:0> transitions from '0000' to '1111'. This parameter is characterized, but not tested in manufacturing.

4: The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.

TABLE 29-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

29.2 AC Characteristics and Timing Parameters

The information contained in this section defines PIC32MX1XX/2XX AC characteristics and timing parameters.

FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 29-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

FIGURE 29-2: EXTERNAL CLOCK TIMING

TABLE 29-15: EXTERNAL CLOCK TIMING REQUIREMENTS

2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin.

3: PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing.

4: This parameter is characterized, but not tested in manufacturing.

TABLE 29-16: PLL CLOCK TIMING SPECIFICATIONS

Note 1: These parameters are characterized, but not tested in manufacturing.

2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula:

$EffectiveJitter = frac{D_CLK}{√{frac{SYSCLK}{CommunicationClock}}}$

For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:

$EffectiveJitter = frac{D_CLK}{√{frac{40}{20}}} = frac{D_CLK}{1.41}$

TABLE 29-17: INTERNAL FRC ACCURACY

TABLE 29-18: INTERNAL LPRC ACCURACY