PCM5102APWR
Stereo Audio DAC with PLLThe PCM5102APWR is a stereo audio dac with pll from Texas Instruments. View the full PCM5102APWR datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
PCM5102APWR shares its datasheet with PCM5102, whose page lists every part number it covers.
Official PCM5102APWR datasheet (PDF) — the source this page was extracted from.
PCM5102APWR Key Specifications
| Parameter | Value |
|---|---|
| Data Interface | PCM |
| Mounting Type | Surface Mount |
| Number of Channels | 2 |
| Operating Temperature | -25°C ~ 85°C |
| Package / Case | 20-TSSOP (0.173", 4.40mm Width) |
| Packaging | MouseReel |
| Resolution (Bits) | 16 b, 24 b, 32 b |
| Sampling Rate | 384k SPS |
| Standard Pack Qty | 2000 |
| Supplier Device Package | 20-TSSOP |
| Type | DAC, Audio |
| Supply Voltage | 1.65V ~ 3.46V |
| Voltage Supply Source | Analog and Digital |
PCM5102APWR Overview
Part: PCM5102A — Texas Instruments
Type: Stereo Audio DAC with PLL
Description: 2.1 VRMS ground-centered line output stereo audio DAC with integrated PLL, 32-bit/384 kHz PCM interface, and 112 dB class dynamic performance in a 20-pin TSSOP package.
Operating Conditions:
- Supply voltage: AVDD 3.0–3.46 V (VCOM mode), CPVDD 3.1–3.46 V, DVDD 1.65–1.95 V (1.8 V) or 3.1–3.46 V (3.3 V)
- Operating junction temperature: -40 to 130 °C
- Max master clock (MCLK): 50 MHz
- Line output load: ≥1 kΩ, ≤10 pF digital output load capacitance
Absolute Maximum Ratings:
- Max supply voltage: 3.9 V (AVDD, CPVDD, DVDD)
- Digital input voltage: 3.9 V (DVDD at 3.3 V), 2.25 V (DVDD at 1.8 V)
- Max junction temperature: 130 °C
- Storage temperature: -65 to 150 °C
Key Specs:
- Output level: 2.1 VRMS ground-centered (Directpath charge pump, no DC blocking capacitors)
- Line output drive: down to 1 kΩ load
- Audio data: 16/24/32-bit, I²S and left-justified formats, up to 384 kHz
- Mute SNR: 120 dB (intelligent soft mute plus analog mute)
- Digital inputs: 1.8 V or 3.3 V failsafe LVCMOS
- Analog supply: 3.3 V single-supply operation
- Clocking: internal PLL generates SCK from BCK, so no MCLK is needed
Features:
- Ultra low out-of-band noise
- Integrated high-performance audio PLL with BCK reference
- Direct line-level 2.1 VRMS output; no DC blocking capacitors required
- Intelligent muting system with soft up/down ramp
- Automatic power-save mode when LRCK and BCK stop
- Clock error and PowerSense undervoltage protection
- Hardware pin configuration
- AEC-Q100 qualified (Q1 devices)
Applications:
- A/V receivers, DVD and BD players
- Automotive infotainment and telematics
- HDTV receivers
- Aftermarket automotive amplifiers
Package:
- TSSOP (20), 5.50 mm × 4.40 mm
PCM5102APWR Features
- 1 · Ultra Low Out-of-Band Noise
- Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally
- Direct Line Level 2.1-VRMS Output
- No DC Blocking Capacitors Required
- Line Level Output Down to 1K Ω
- Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR
- Accepts 16-, 24-, and 32-Bit Audio Data
- PCM Data Formats: I 2 S, Left-Justified
- Automatic Power-Save Mode When LRCK And BCK Are Deactivated
- 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
- Simple Configuration Using Hardware Pins
- Single-Supply Operation: 14
- -3.3 V Analog, 1.8 V or 3.3 V Digital
- Qualified in Accordance with AEC-Q100
PCM5102APWR Applications
- A/V Receivers, DVD, BD Players
- Automotive Infotainment and Telematics
- HDTV Receivers
- Aftermarket Automotive Amplifiers
PCM5102APWR Pin Configuration
| PIN - NAME | PIN - NO. | TYPE | DESCRIPTION |
|---|---|---|---|
| AGND | 9 | - | Analog ground |
| AVDD | 8 | P | Analog power supply, 3.3 V |
| BCK | 13 | I | Audio data bit clock input (1) |
| CAPM | 4 | O | Charge pump flying capacitor terminal for negative rail |
| CAPP | 2 | O | Charge pump flying capacitor terminal for positive rail |
| CPGND | 3 | - | Charge pump ground |
| CPVDD | 1 | P | Charge pump power supply, 3.3 V |
| DEMP | 10 | I | De-emphasis control for 44.1-kHz sampling rate (1) : Off (Low) / On (High) |
| DGND | 19 | - | Digital ground |
| DIN | 14 | I | Audio data input (1) |
| DVDD | 20 | P | Digital power supply, 1.8 V or 3.3 V |
| FLT | 11 | I | Filter select : Normal latency (Low) / Low latency (High) |
| FMT | 16 | I | Audio format selection : I 2 S (Low) / Left-justified (High) |
| LDOO | 18 | P | Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal |
| LRCK | 15 | I | Audio data word clock input (1) |
| OUTL | 6 | O | Analog output from DAC left channel |
| OUTR | 7 | O | Analog output from DAC right channel |
| SCK | 12 | I | System clock input (1) |
| VNEG | 5 | O | Negative charge pump rail terminal for decoupling, -3.3 V |
| XSMT | 17 | I | Soft mute control (1) : Soft mute (Low) / soft un-mute (High) |
PCM5102APWR Electrical Characteristics
Q1 Automotive grade devices are specified for TA = -40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
| PARAMETER - Resolution | TEST CONDITIONS - Resolution | MIN - 16 | TYP - 24 | MAX - 32 | UNIT - Bits | |
|---|---|---|---|---|---|---|
| Data Format (PCM Mode) | Data Format (PCM Mode) | Data Format (PCM Mode) | Data Format (PCM Mode) | Data Format (PCM Mode) | Data Format (PCM Mode) | Data Format (PCM Mode) |
| Audio data bit length | 16 | 24 | 32 | Bits | ||
| f S (1) | Sampling frequency | 8 | 384 | kHz | ||
| f SCK | System clock frequency | Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 | 50 | MHz | ||
| Digital Input/Output for non-Q1 Consumer Grade Devices | Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible | Digital Input/Output for non-Q1 Consumer Grade Devices | Digital Input/Output for non-Q1 Consumer Grade Devices | Digital Input/Output for non-Q1 Consumer Grade Devices | Digital Input/Output for non-Q1 Consumer Grade Devices | Digital Input/Output for non-Q1 Consumer Grade Devices |
| V IH | Input logic level | 0.7×DV DD | V | |||
| V IL | 0.3×DV DD | |||||
| I IH | Input logic current | V IN = V DD | 10 | μA | ||
| I IL | V IN = 0 V | -10 | ||||
| V OH | Output logic level | I OH = -4 mA | 0.8×DV DD | V | ||
| V OL | Output logic level | I OL = 4 mA | 0.22×DV DD | |||
| Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | |
| V IH | Input logic level | 0.7×DV DD | ||||
| V IL | 0.3×DV DD | V | ||||
| I IH | Input logic current | V IN = V DD | 10 | |||
| I IL | V IN = 0 V | -10 | μA | |||
| V OH | Output logic level | I OH = -2 mA | 0.8×DV DD | |||
| V OL | Output logic level | I OL = 2 mA | 0.22×DV DD | V | ||
| Digital Input/Output for Q1 Automotive Grade Devices | Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible | Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible | Digital Input/Output for Q1 Automotive Grade Devices | Digital Input/Output for Q1 Automotive Grade Devices | Digital Input/Output for Q1 Automotive Grade Devices | Digital Input/Output for Q1 Automotive Grade Devices |
| V IH | Input logic level | 0.7×DV DD | ||||
| V IL | 0.3×DV DD | V | ||||
| I IH | Input logic current | V IN = V DD | 10 | μA | ||
| I IL | V IN = 0 V | -10 | ||||
| V OH | Output logic level | I OH = -4 mA | 0.8×DV DD | |||
| V OL | I OL = 4 mA | 0.22×DV DD | V | |||
| Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | Logic family 1.8 V LVCMOS compatible | |
| V IH | Input logic level | 0.7×DV DD | ||||
| V IL | 0.3×DV DD | V | ||||
| I IH | Input logic current | V IN = V DD | 10 | |||
| I IL | V IN = 0 V | -10 | μA | |||
| V OH | Output logic level | I OH = -2 mA | 0.8×DV DD | |||
| V OL | I OL = 2 mA | 0.3×DV DD | V |
SLAS859C -MAY 2012-REVISED MAY 2015
PCM5102APWR Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage | AVDD, CPVDD, DVDD | -0.3 | 3.9 | V |
| Supply voltage | LDO with DVDD at 1.8 V | -0.3 | 2.25 | V |
| Digital input voltage | DVDD at 1.8 V | -0.3 | 2.25 | V |
| Digital input voltage | DVDD at 3.3 V | -0.3 | 3.9 | V |
| Analog input voltage | Analog input voltage | -0.3 | 3.9 | V |
| Operating junction temperature range | Operating junction temperature range | -40 | 130 | °C |
| Storage temperature, T stg | Storage temperature, T stg | -65 | 150 | °C |
PCM5102APWR Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|
| AVDD | Analog power supply voltage range | Referenced to AGND (1) | VCOM mode | 3 | 3.3 | 3.46 | V |
| AVDD | Referenced to AGND (1) | VREF mode | 3.2 | 3.3 | 3.46 | V | |
| DVDD | Digital power supply voltage range | Referenced to DGND (1) | 1.8 V DVDD | 1.65 | 1.8 | 1.95 | V |
| DVDD | Referenced to DGND (1) | 3.3 V DVDD | 3.1 | 3.3 | 3.46 | V | |
| CPVDD | Charge pump supply voltage range | Referenced to CPGND (1) | Referenced to CPGND (1) | 3.1 | 3.3 | 3.46 | V |
| MCLK | Master clock frequency | 50 | MHz | ||||
| LOL, | Stereo line output load resistance | LOR | LOR | 1 | 10 | k Ω | |
| C LOUT | Digital output load capacitance | 10 | pF | ||||
| T J | Operating junction temperature range | -40 | 130 | °C |
PCM5102APWR Thermal Information
| THERMAL METRIC (1) | THERMAL METRIC (1) | PW 20 PINS | UNIT |
|---|---|---|---|
| R θ JA | Junction-to-ambient thermal resistance | 91.2 | °C/W |
| R θ JC(top) | Junction-to-case (top) thermal resistance | 25.3 | °C/W |
| R θ JB | Junction-to-board thermal resistance | 42 | °C/W |
| ψ JT | Junction-to-top characterization parameter | 1 | °C/W |
| ψ JB | Junction-to-board characterization parameter | 41.5 | °C/W |
| R θ JC(bot) | Junction-to-case (bottom) thermal resistance | - | °C/W |
PCM5102APWR Typical Application
Figure 33. Simplified Schematic, Hardware-Controlled Subsystem
PCM5102APWR Package Information
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| PCM5102 | Texas Instruments | TSSOP-20 |
| PCM5102A | Texas Instruments | TSSOP-20 |
| PCM5102A-Q1 | Texas Instruments | TSSOP-20 |
| PCM5102APW | Texas Instruments | 20-TSSOP (0.173", 4.40mm Width) |
Other ADC / DAC
- ADS1115 – Texas Instruments, Analog-to-Digital Converter
- PCM1865DBTR – Texas Instruments, Audio ADC
- AD5065 – Analog Devices, Digital-to-Analog Converter
- AD5671R – Analog Devices, Digital-to-Analog Converter (DAC)
- AD5675R – Analog Devices, Digital-to-Analog Converter (DAC)
- AD5675RACPZ-REEL7 – Analog Devices, Digital-to-Analog Converter (DAC)
- AD5675RACPZ-RL – Analog Devices, Digital-to-Analog Converter (DAC)
- AD5675RARUZ – Analog Devices, Digital-to-Analog Converter (DAC)
All ADC / DAC datasheetsAll Texas Instruments datasheets (2,442)
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
Ask your AI agent about the PCM5102APWR
Connect SheetsData to Claude, Cursor, Codex or any MCP client and your agent reads this datasheet for you: pinout, limits, register maps and design checks, with the numbers taken from the PDF.
claude mcp add --transport http sheetsdata https://mcp.sheetsdata.com/mcp
Then ask: "Can the PCM5102APWR run from my 12 V rail? Check it against the datasheet limits."
Create a free account $2 of usage every month, no card needed.