PCM5102APWR

Part: PCM5100A, PCM5101A, PCM5102A, PCM5100A-Q1, PCM5101A-Q1, PCM5102A from Texas Instruments

Type: Audio Stereo DAC

Key Specs:

• Output Voltage: 2.1 VRMS
• Dynamic Range: Up to 112 dB (PCM5102A)
• Signal-to-Noise Ratio (SNR): Up to 112 dB (PCM5102A)
• Total Harmonic Distortion (THD): Down to -93 dB (PCM5102A)
• PCM Interface: 32-bit, 384 kHz
• Analog Supply Voltage: 1.4 V to 3.3 V
• Digital Supply Voltage: 1.8 V or 3.3 V
• Minimum Load Resistance: 1 kΩ
• Mute SNR: 120 dB

Features:

• Ultra-low out-of-band noise
• Integrated audio PLL with BCK reference
• Direct line-level 2.1 VRMS output, no DC-blocking capacitors required
• Supports loads down to 1 kΩ
• Smart mute system with 120 dB mute SNR
• Receives 16, 24, and 32-bit audio data (I²S, left-aligned)
• Automatic power-save mode
• 1.8V or 3.3V fault-tolerant LVCMOS digital inputs
• Easy hardware pin configuration
• Single supply operation
• AEC-Q100 compliant (for -Q1 variants)
• DirectPath™ charge pump technology
• Integrated PLL eliminates system clock (MCLK)
• Smart clock error and PowerSense undervoltage protection

Applications:

• A/V receivers, DVD, BD players
• Automotive infotainment systems and telematics
• HDTV receivers
• Automotive aftermarket amplifiers

Package:

• TSSOP (20): 5.50mm x 4.40mm

注

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Pin Functions

• NAME
• AGND
• AVDD
• BCK
• CAPM
• CAPP
• CPGND
• CPVDD
• DEMP
• DGND
• DIN
• DVDD
• FLT
• FMT
• LDOO
• LRCK
• OUTL
• OUTR
• SCK
• VNEG
• XSMT

(1) Failsafe LVCMOS Schmitt trigger input

ZHCSA60C –MAY 2012–REVISED MAY 2015 www.ti.com.cn

Q1 Automotive grade devices are specified for T^A = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at T^A = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, f^S = 48 kHz, system clock = 512 f^S and 24-bit data unless otherwise noted.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution Data Format (PCM Mode)		16	24	32	Bits
	Audio data bit length		16	24	32	Bits
(1) fS	Sampling frequency		8		384	kHz
fSCK	System clock frequency Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible	Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072			50	MHz
VIH	Input logic level		0.7×DVDD			V
VIL					0.3×DVDD
IIH		VIN = VDD			10
IIL	Input logic current	VIN = 0 V			–10	μA
VOH		IOH = –4 mA	0.8×DVDD
VOL	Output logic level Logic family 1.8 V LVCMOS compatible	IOL = 4 mA			0.22×DVDD	V
VIH			0.7×DVDD
VIL	Input logic level				0.3×DVDD	V
IIH		VIN = VDD			10
IIL	Input logic current	VIN = 0 V			–10	μA
VOH		IOH = –2 mA	0.8×DVDD
VOL	Output logic level	IOL = 2 mA			0.22×DVDD	V
Digital Input/Output for Q1 Automotive Grade Devices	Logic family: 3.3 V LVCMOS compatible
VIH			0.7×DVDD
VIL	Input logic level				0.3×DVDD	V
IIH		VIN = VDD			10
IIL	Input logic current	VIN = 0 V			–10	μA
VOH		IOH = –4 mA	0.8×DVDD
VOL	Output logic level Logic family 1.8 V LVCMOS compatible	IOL = 4 mA			0.22×DVDD	V
VIH			0.7×DVDD
VIL	Input logic level				0.3×DVDD	V
IIH		VIN = VDD			10
IIL	Input logic current	VIN = 0 V			–10	μA
VOH		IOH = –2 mA	0.8×DVDD
VOL	Output logic level	IOL = 2 mA			0.3×DVDD	V

ZHCSA60C –MAY 2012–REVISED MAY 2015 www.ti.com.cn

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	AVDD, CPVDD, DVDD	–0.3	3.9
Supply voltage	LDO with DVDD at 1.8 V	–0.3	2.25
Supply voltage	DVDD at 1.8 V	–0.3	2.25	V
Digital input voltage	DVDD at 3.3 V	–0.3	3.9
Analog input voltage		–0.3	3.9
Operating junction temperature range		–40	130	°C
Storage temperature, Tstg		–65	150	°C

				MIN	NOM	MAX	UNIT
AVDD	Analog power supply voltage range	Referenced to AGND(1)	VCOM mode	3	3.3	3.46	V
			VREF mode	3.2	3.3	3.46
	Digital power supply voltage range	Referenced to DGND(1)	1.8 V DVDD	1.65	1.8	1.95	V
DVDD			3.3 V DVDD	3.1	3.3	3.46
CPVDD	Charge pump supply voltage range	Referenced to CPGND(1)		3.1	3.3	3.46	V
MCLK	Master clock frequency					50	MHz
LOL, LOR	Stereo line output load resistance			1	10		kΩ
CLOUT	Digital output load capacitance				10		pF
TJ	Operating junction temperature range			–40		130	°C

(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2 V max, for any combination of ground signals.

THERMAL METRIC(1)		PW	UNIT
		20 PINS
RθJA	Junction-to-ambient thermal resistance	91.2	°C/W
RθJC(top)	Junction-to-case (top) thermal resistance	25.3	°C/W
RθJB	Junction-to-board thermal resistance	42	°C/W
ψJT	Junction-to-top characterization parameter	1	°C/W
ψJB	Junction-to-board characterization parameter	41.5	°C/W
RθJC(bot)	Junction-to-case (bottom) thermal resistance	—	°C/W

www.ti.com.cn ZHCSA60C –MAY 2012–REVISED MAY 2015