PCM5102APW

Part: PCM510xA — Texas Instruments

Type: Stereo Digital-to-Analog Converter (DAC)

Description: A monolithic CMOS integrated circuit family featuring a stereo DAC with an integrated PLL, DirectPath™ charge pump technology for 2.1 VRMS center-grounded output, and support for 16, 24, and 32-bit audio data with I2S and left-aligned PCM data styles.

Operating Conditions:

• Supply voltage: 3–3.46 V (Analog), 1.65–1.95 V or 3.1–3.46 V (Digital), 3.1–3.46 V (Charge Pump)
• Operating temperature: -40 to 130 °C
• Master clock frequency: Up to 50 MHz
• Stereo line output load resistance: 1 kΩ (min)

Absolute Maximum Ratings:

• Max supply voltage: 3.9 V (AVDD, CPVDD, DVDD)
• Max junction/storage temperature: 130 °C (Operating Junction), 150 °C (Storage)

Key Specs:

• Dynamic Range (PCM5102A): 112 dB
• SNR (PCM5102A): 112 dB
• THD+N at -1 dBFS (PCM5102A): -93 dB
• Full-scale single-ended output: 2.1 VRMS (GND center)
• Sampling frequency: 8 kHz to 384 kHz
• Digital input voltage (DVDD at 1.8 V): -0.3 to 2.25 V
• Digital input voltage (DVDD at 3.3 V): -0.3 to 3.9 V
• ESD HBM: ±2000 V

Features:

• Ultra-low out-of-band noise
• High-performance integrated audio PLL with BCK reference
• Direct line-level 2.1 VRMS output, no DC-blocking capacitors required
• Line-level output supports loads down to 1 kΩ
• Smart mute system with soft ramp/down and analog mute for 120dB mute SNR
• Receives 16, 24, and 32-bit audio data
• PCM data styles: I2S, left-aligned
• Automatic power-save mode when LRCK and BCK are invalid
• 1.8V or 3.3V fault-tolerant low-voltage CMOS (LVCMOS) digital inputs
• Easy configuration using hardware pins
• Single supply operation
• AEC-Q100 compliant

Applications:

• A/V receivers, DVD, BD players
• Automotive infotainment systems and telematics
• HDTV receivers
• Automotive aftermarket amplifiers

Package:

• TSSOP (20) - 5.50mm x 4.40mm

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

PIN	PIN	TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
AGND	9	-	Analog ground
AVDD	8	P	Analog power supply, 3.3 V
BCK	13	I	Audio data bit clock input (1)
CAPM	4	O	Charge pump flying capacitor terminal for negative rail
CAPP	2	O	Charge pump flying capacitor terminal for positive rail
CPGND	3	-	Charge pump ground
CPVDD	1	P	Charge pump power supply, 3.3 V
DEMP	10	I	De-emphasis control for 44.1-kHz sampling rate (1) : Off (Low) / On (High)
DGND	19	-	Digital ground
DIN	14	I	Audio data input (1)
DVDD	20	P	Digital power supply, 1.8 V or 3.3 V
FLT	11	I	Filter select : Normal latency (Low) / Low latency (High)
FMT	16	I	Audio format selection : I 2 S (Low) / Left-justified (High)
LDOO	18	P	Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal
LRCK	15	I	Audio data word clock input (1)
OUTL	6	O	Analog output from DAC left channel
OUTR	7	O	Analog output from DAC right channel
SCK	12	I	System clock input (1)
VNEG	5	O	Negative charge pump rail terminal for decoupling, -3.3 V
XSMT	17	I	Soft mute control (1) : Soft mute (Low) / soft un-mute (High)

Q1 Automotive grade devices are specified for TA = -40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution		16	24	32	Bits
Data Format (PCM Mode)	Data Format (PCM Mode)	Data Format (PCM Mode)	Data Format (PCM Mode)	Data Format (PCM Mode)	Data Format (PCM Mode)	Data Format (PCM Mode)
	Audio data bit length		16	24	32	Bits
f S (1)	Sampling frequency		8		384	kHz
f SCK	System clock frequency	Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072			50	MHz
Digital Input/Output for non-Q1 Consumer Grade Devices	Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible	Digital Input/Output for non-Q1 Consumer Grade Devices	Digital Input/Output for non-Q1 Consumer Grade Devices	Digital Input/Output for non-Q1 Consumer Grade Devices	Digital Input/Output for non-Q1 Consumer Grade Devices	Digital Input/Output for non-Q1 Consumer Grade Devices
V IH	Input logic level		0.7×DV DD
V IL					0.3×DV DD	V
I IH	Input logic current	V IN = V DD			10	μA
I IL		V IN = 0 V			-10
V OH	Output logic level	I OH = -4 mA	0.8×DV DD			V
V OL		I OL = 4 mA			0.22×DV DD
	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible
V IH	Input logic level		0.7×DV DD
V IL					0.3×DV DD	V
I IH	Input logic current	V IN = V DD			10
I IL		V IN = 0 V			-10	μA
V OH	Output logic level	I OH = -2 mA	0.8×DV DD
V OL		I OL = 2 mA			0.22×DV DD	V
Digital Input/Output for Q1 Automotive Grade Devices	Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible	Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible	Digital Input/Output for Q1 Automotive Grade Devices	Digital Input/Output for Q1 Automotive Grade Devices	Digital Input/Output for Q1 Automotive Grade Devices	Digital Input/Output for Q1 Automotive Grade Devices
V IH	Input logic level		0.7×DV DD
V IL					0.3×DV DD	V
I IH		V IN = V DD			10
I IL	Input logic current	V IN = 0 V			-10	μA
V OH	Output logic level	I OH = -4 mA	0.8×DV DD			V
V OL		I OL = 4 mA			0.22×DV DD
	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible	Logic family 1.8 V LVCMOS compatible
V IH	Input logic level		0.7×DV DD
V IL					0.3×DV DD	V
I IH	Input logic current	V IN = V DD			10
I IL V		V IN = 0 V I OH = -2 mA	0.8×DV DD		-10	μA
OH V OL	Output logic level	I OL = 2 mA			0.3×DV DD	V

ZHCSA60C -MAY 2012-REVISED MAY 2015

ZHCSA60C -MAY 2012-REVISED MAY 2015

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	AVDD, CPVDD, DVDD	-0.3	3.9	V
Supply voltage	LDO with DVDD at 1.8 V	-0.3	2.25	V
Digital input voltage	DVDD at 1.8 V	-0.3	2.25	V
Digital input voltage	DVDD at 3.3 V	-0.3	3.9	V
Analog input voltage	Analog input voltage	-0.3	3.9	V
Operating junction temperature range	Operating junction temperature range	-40	130	°C
Storage temperature, T stg	Storage temperature, T stg	-65	150	°C

				MIN	NOM	MAX	UNIT
AVDD	Analog power supply voltage range	Referenced to AGND (1)	VCOM mode	3	3.3	3.46	V
AVDD		Referenced to AGND (1)	VREF mode	3.2	3.3	3.46	V
DVDD	Digital power supply voltage range	Referenced to DGND (1)	1.8 V DVDD	1.65	1.8	1.95	V
DVDD		Referenced to DGND (1)	3.3 V DVDD	3.1	3.3	3.46	V
CPVDD	Charge pump supply voltage range	Referenced to CPGND (1)	Referenced to CPGND (1)	3.1	3.3	3.46	V
MCLK	Master clock frequency					50	MHz
LOL,	Stereo line output load resistance	LOR	LOR	1	10		k Ω
C LOUT	Digital output load capacitance				10		pF
T J	Operating junction temperature range			-40		130	°C

THERMAL METRIC (1)	THERMAL METRIC (1)	PW 20 PINS	UNIT
R θ JA	Junction-to-ambient thermal resistance	91.2	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance	25.3	°C/W
R θ JB	Junction-to-board thermal resistance	42	°C/W
ψ JT	Junction-to-top characterization parameter	1	°C/W
ψ JB	Junction-to-board characterization parameter	41.5	°C/W
R θ JC(bot)	Junction-to-case (bottom) thermal resistance	-	°C/W

Figure 33. Simplified Schematic, Hardware-Controlled Subsystem