MR4A16BMA35R

Part: MR4A16B — Everspin Technologies

Type: Magnetoresistive Random Access Memory (MRAM)

Description: 16,777,216-bit (1M x 16) MRAM device offering SRAM compatible 35 ns read/write timing with unlimited endurance and data non-volatility for over 20 years, featuring internal single bit error correction code.

Operating Conditions:

• Supply voltage: 3.0–3.6 V
• Operating temperature: 0 to +70 °C (suffix-dependent — see Table 4.1 for grade-specific ranges)
• Write inhibit voltage: 2.5–3.0 V

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max output current per pin: ±20 mA
• Max junction/storage temperature: 150 °C

Key Specs:

• Read cycle time: 35 ns
• Write cycle time: 35 ns
• Address access time: 35 ns
• AC active supply current - read modes (I OUT = 0 mA, V DD = max): 68 mA
• AC active supply current - write modes (V DD = max): 180 mA
• CMOS standby current (E ≥ V DD - 0.2V and V In ≤ V SS + 0.2V or ≥ V DD - 0.2 V): 9 mA
• Data non-volatility: >20 years at temperature
• Input leakage current: ±1 μA
• Output leakage current: ±1 μA

Features:

• +3.3 Volt power supply
• SRAM compatible timing
• Unlimited read & write endurance
• Data always non-volatile for >20-years at temperature
• RoHS-compliant small footprint BGA and TSOP2 package
• AEC-Q100 Grade 1 option in TSOP2 package
• Internal single bit error correction code with 7 ECC parity bits for every 64 data bits
• Low-voltage inhibit circuitry for power loss protection

Applications:

• Systems requiring permanent storage and quick retrieval of critical data and programs

Package:

• 48-pin Ball Grid Array (BGA)
• 54-pin Thin Small Outline Package (TSOP2)

• +3.3 Volt power supply
• Fast 35 ns read/write cycle
• SRAM compatible timing
• Unlimited read & write endurance
• Data always non-volatile for >20-years at temperature
• RoHS-compliant small footprint BGA and TSOP2 package
• AEC-Q100 Grade 1 option in TSOP2 package.

MR4A16BMA35R – 48-Pin BGA Pinout

Notes

• Power pins: VDD (pin 25), VSS (pins 20, 26, 30)
• No Connect pins: NC (pins 6, 38), DC (pin 27)
• Address bus: A0–A19 (20 address lines for 1M × 16 memory)
• Data bus: DQ0–DQ15 (16-bit data I/O)
• Control signals: E (Chip Enable), W (Write Enable), G (Output Enable), UB (Upper Byte Enable), LB (Lower Byte Enable)
• All address and control inputs are active-low or follow standard SRAM logic levels
• DQ3 appears twice in the pin diagram (pins 19 and 24); this reflects the source material as shown

Table 2.4 Power Supply Characteristics

1 All active current measurements are measured with one address transition per cycle and at minimum cycle time.

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field greater than the maximum field intensity specified in the maximum ratings.

Table 2.1 Absolute Maximum Ratings 1

Table 2.2 Operating Conditions