MPXV7002GC6U/GC6T1
MPXV7002 Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated
Integrated Silicon Pressure SensorThe MPXV7002GC6U/GC6T1 is a integrated silicon pressure sensor from NXP USA Inc.. MPXV7002 Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated. View the full MPXV7002GC6U/GC6T1 datasheet below including key specifications, absolute maximum ratings.
Manufacturer
NXP USA Inc.
Category
SensorsKey Specifications
| Parameter | Value |
|---|---|
| Accuracy | ±5% |
| Applications | Board Mount |
| Features | Temperature Compensated |
| Maximum Pressure | ±10.88PSI (±75kPa) |
| Mounting Type | Surface Mount |
| Operating Pressure | ±0.29PSI (±2kPa) |
| Operating Temperature | 10°C ~ 60°C |
| Output | 0.5 V ~ 4.5 V |
| Output Type | Analog Voltage |
| Package / Case | 8-BSOP (0.475\", 12.06mm Width) Dual Ports, Same Side |
| Port Size | Male - 0.13\" (3.3mm) Tube, Dual |
| Port Style | Barbed |
| Pressure Type | Differential |
| Supplier Device Package | 8-SOP |
| Termination Style | Gull Wing |
| Supply Voltage | 4.75V ~ 5.25V |
Overview
Part: NXP Semiconductors MPXV7002
Type: Integrated Silicon Pressure Sensor
Description: A -2 to +2 kPa integrated silicon pressure sensor with on-chip signal conditioning, temperature compensation, and calibration, providing a 0.5 to 4.5 V analog output.
Operating Conditions:
- Supply voltage: 4.75–5.25 Vdc
- Operating temperature: 10 to 60 °C
- Pressure range: –2.0 to 2.0 kPa
Absolute Maximum Ratings:
- Max pressure (P1 > P2): 75 kPa
- Max junction/storage temperature: –30 to +100 °C
Key Specs:
- Pressure Range (POP): –2.0 to 2.0 kPa
- Supply Current (Io): 10 mAdc (Max)
- Pressure Offset (Voff): 0.25 to 0.75 Vdc (at VS = 5.0 Vdc, 10 to 60°C)
- Full Scale Output (VFSO): 4.25 to 4.75 Vdc (at VS = 5.0 Vdc, 10 to 60°C)
- Full Scale Span (VFSS): 3.5 to 4.5 Vdc (at VS = 5.0 Vdc, 10 to 60°C)
- Accuracy: ±2.5% (Typ), ±6.25% (Max) of VFSS (10 to 60°C)
- Sensitivity (V/P): 1.0 V/kPa (Typ)
- Response Time (tR): 1.0 ms (Typ)
Features:
- 2.5% Typical Error over +10°C to +60°C with Auto Zero
- 6.25% Maximum Error over +10°C to +60°C without Auto Zero
- Ideally Suited for Microprocessor or Microcontroller-Based Systems
- Thermoplastic (PPS) Surface Mount Package
- Temperature Compensated over +10° to +60°C
- Patented Silicon Shear Stress Strain Gauge
- Available in Differential and Gauge Configurations
Applications:
Package:
- Case 482A (Small Outline Package)
- Case 1369 (Small Outline Package)
- Case 1351 (Small Outline Package)
Features
- 2.5% Typical Error over +10°C to +60°C with Auto Zero
- 6.25% Maximum Error over +10°C to +60°C without Auto Zero
- Ideally Suited for Microprocessor or Microcontroller-Based Systems
- Thermoplastic (PPS) Surface Mount Package
- Temperature Compensated over +10° to +60°C
- Patented Silicon Shear Stress Strain Gauge
- Available in Differential and Gauge Configurations
Applications
Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct footprint, the packages will self align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads.
Figure 5. Small Outline Package Footprint
Absolute Maximum Ratings
Table 2. Maximum Ratings(1)
| Rating | Symbol | Value | Unit |
|---|---|---|---|
| Maximum Pressure (P1 > P2) | Pmax | 75 | kPa |
| Storage Temperature | Tstg | –30 to +100 | °C |
| Operating Temperature | TA | 10 to 60 | °C |
1.Exposure beyond the specified limits may cause permanent damage or degradation to the device.
Figure 1 shows a block diagram of the internal circuitry integrated on a pressure sensor chip.
Figure 1. Integrated Pressure Sensor Schematic
3 On-Chip Temperature Compensation, Calibration and Signal Conditioning
The performance over temperature is achieved by integrating the shear-stress strain gauge, temperature compensation, calibration and signal conditioning circuitry onto a single monolithic chip.
Figure 2 illustrates the Differential or Gauge configuration in the basic chip carrier (Case 482). A gel die coat isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the sensor diaphragm.
The MPXV7002 series pressure sensor operating characteristics, and internal reliability and qualification tests are based on use of dry air as the pressure media. Media, other than dry air, may have adverse effects on sensor performance and long-term reliability. Contact the factory for information regarding media compatibility in your application.
Figure 3 shows the recommended decoupling circuit for interfacing the integrated sensor to the A/D input of a microprocessor or microcontroller. Proper decoupling of the power supply is recommended.
Figure 4 shows the sensor output signal relative to pressure input. Typical, minimum, and maximum output curves are shown for operation over a temperature range of 10° to 60°C using the decoupling circuit shown in Figure 3. The output will saturate outside of the specified pressure range.
Figure 2. Cross-Sectional Diagram SOP (not to scale)
Figure 3. Recommended Power Supply Decoupling and Output Filtering (For additional output filtering, please refer to Application Note AN1646.)
Figure 4. Output versus Pressure Differential
4 Pressure (P1)/Vacuum (P2) Side Identification Table
NXP designates the two sides of the pressure sensor as the Pressure (P1) side and the Vacuum (P2) side. The Pressure (P1) side is the side containing a gel die coat which protects the die from harsh media.
The Pressure (P1) side may be identified by using the following table:
| Part Number | Case Type | Pressure (P1) Side Identifier |
|---|---|---|
| MPXV7002GC6U/GC6T1 | 482A-01 | Side with Port Attached |
| MPXV7002GP | 1369-01 | Side with Port Attached |
| MPXV7002DP | 1351-01 | Side with Part Marking |
Package Information
NOTES:
-
- DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
-
- CONTROLLING DIMENSION: INCH.
-
- DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
-
- MAXIMUM MOLD PROTRUSION 0.15 (0.006). 5. ALL VERTICAL SURFACES 5 TYPICAL DRAFT.
| INCHES | MILLIMETERS | |||
|---|---|---|---|---|
| DIM | MIN | MAX | MIN | MAX |
| A | 0.415 | 0.425 | 9 10.54 10.7 | |
| B | 0.415 | 0.425 | 9 10.54 10.7 | |
| C | 0.500 | 0.520 | 1 12.70 13.2 | |
| D | 0.038 | 0.042 | 7 0.96 1.0 | |
| G | 0.100 BSC | 2.54 BSC | ||
| H | 0.002 | 0.010 | 0.05 | 0.25 |
| J | 0.009 | 0.011 | 0.23 | 0.28 |
| K | 0.061 | 0.071 | 1.55 | 1.80 |
| M | 0 | 7 | 0 | 7 |
| N | 0.444 | 0.448 | 11.28 | 11.38 |
| S | 0.709 | 0.725 | 18.01 | 18.41 |
| V | 0.245 | 0.255 | 6.22 | 6.48 |
| W | 0.115 | 0.125 | 2.92 | 3.17 |
DATE 05/13/98
CASE 482A-01 ISSUE A SMALL OUTLINE PACKAGE
| NXP SEMICONDUCTORS N.V. ALL RIGHTS RESERVED | MECHANICAL OUTLINE | PRINT VERSION NO | OT TO SCALE | |
|---|---|---|---|---|
| TITLE: | DOCUMEN | NT NO: 98ASA99255D | REV: B | |
| 8 LD SNSR, DUAL | PORT | STANDAF | RD: NON-JEDEC | |
| S0T1693 | 3-1 | 14 MAR 2016 |
CASE 1351-01 ISSUE A SMALL OUTLINE PACKAGE
| STYLE 1: | STYLE 2: | |
|---|---|---|
| PIN 1: | GND | PIN 1: |
| PIN 2: | +Vout | PIN 2: |
| PIN 3: | Vs | PIN 3: |
| PIN 4: | -Vout | PIN 4: |
| PIN 5: | N/C | PIN 5: |
| PIN 6: | N/C | PIN 6: |
| PIN 7: | N/C | PIN 7: |
| PIN 8: | N/C | PIN 8: |
| NXP SEMICONDUCTORS N. V. ALL RIGHTS RESERVED | MECHANICAL OUTLINE | |
| ------------------------------------------------- | -------------------- | --------- |
| TITLE: | DOCUMEN | |
| 8 LD SNSR, DUAL | DUAL PORT | |
| S0T1693 |
CASE 1351-01 ISSUE A SMALL OUTLINE PACKAGE
MPXV7002
| NXP SEMICONDUCTORS N. V. ALL RIGHTS RESERVED | MECHANICAL OUTLINE | PRINT VERSION NO | T TO SCALE | |
|---|---|---|---|---|
| TITLE: | DOCUMEN | NT NO: 98ASA99303D | REV: E | |
| 8 LD SOP, SIDE PO | ORT | STANDAF | RD: NON-JEDEC | |
| o Eb oor, older older | S0T1693-3 | 14 MAR 2016 |
CASE 1369-01 ISSUE B SMALL OUTLINE PACKAGE
| INC | HES | MIL | LIMETERS | INCHES | MILLI | METERS | |||
|---|---|---|---|---|---|---|---|---|---|
| DIM | MIN | MAX | MIN | MAX | DIM | MIN | MAX | MIN | MAX |
| A | .300 | .330 | 7.62 | 8.38 | θ | 0. | 7. | 0. | 7. |
| A1 | .002 | .010 | 0.05 | 0.25 | _ | ||||
| Ь | .038 | .042 | 0.96 | 1.07 | _ | ||||
| D | .465 | .485 | 11.81 | 12.32 | _ | ||||
| E | .717 | BSC | 18 | .21 BSC | _ | ||||
| E1 | .465 | .485 | 11.81 | 12.32 | _ | ||||
| e | .100 | BSC | 2. | 54 BSC | _ | ||||
| F | .245 | .255 | 6.22 | 6.47 | _ | ||||
| K | .120 | .130 | 3.05 | 3.30 | _ | ||||
| L | .061 | .071 | 1.55 | 1.80 | _ | ||||
| M | .270 | .290 | 6.86 | 7.36 | _ | ||||
| N | .080 | .090 | 2.03 | 2.28 | _ | ||||
| P | .009 | .011 | 0.23 | 0.28 | _ | ||||
| T | .115 A NVD SEMIC | .125 MINITARS NI V | 2.92 | 3.17 | _ | ||||
| © NXP SEMICONDUCTORS N. V. ALL RIGHTS RESERVED MECHANICAL OU | TLINE | PRINT VER | SION NOT | TO SCALE | |||||
| TITI | TITLE: 8 LD SOP, SIDE PORT | DOCUMENT NO: 98ASA99303D REV: E STANDARD: NON-JEDEC S0T1693 | 3–3 | 14 | MAR 2016 |
CASE 1369-01 ISSUE B SMALL OUTLINE PACKAGE
MPXV7002
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| MPXV7002 | NXP USA Inc. | — |
| MPXV7002DP | NXP USA Inc. | 8-BSOP (0.475", 12.06mm Width) Dual Ports, Same Side |
| MPXV7002DPT1 | NXP USA Inc. | — |
| MPXV7002GC6T1 | NXP USA Inc. | — |
| MPXV7002GC6U | NXP USA Inc. | — |
| MPXV7002GP | NXP USA Inc. | — |
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