MAX32660GTP

Part: MAX32660 from Maxim Integrated

Type: Arm Cortex-M4 Processor with FPU-Based Microcontroller (MCU)

Key Specs:

• Flash Memory: 256KB
• SRAM: 96KB
• Internal Oscillator: up to 96MHz
• Active Current: 85μA/MHz
• VCORE Supply Voltage: 1.1V (typical)
• VDD Supply Voltage: 1.71V to 3.63V
• Operating Temperature: -40°C to +105°C
• Full Memory Retention Power in Backup Mode: 2μA
• Ultra-Low Power RTC: 450nA

Features:

• Arm Cortex-M4 processor with FPU
• Flexible and versatile power management unit
• SPI, UART, and I2C communication support
• Optional bootloader through I2C, UART, or SPI
• 16KB Instruction Cache
• Memory Protection Unit (MPU)
• Low 1.1V VCORE Supply Voltage
• 3.6V GPIO Operating Range
• Internal LDO
• Internal 80kHz Ring Oscillator
• Up to 14 General-Purpose I/O Pins
• I2S
• Four-Channel Standard DMA Controller
• Three 32-Bit Timers
• Watchdog Timer
• CMOS-Level 32.768kHz RTC Output

Applications:

• Sports Watches
• Fitness Monitors
• Wearable Medical Patches
• Portable Medical Devices
• Industrial Sensors
• IoT
• Optical Modules: QSFP-DD, QSFP, 400G

Package:

• 16-bump WLP: 1.6mm x 1.6mm
• 20-pin TQFN-EP: 4mm x 4mm
• 24-pin TQFN-EP: 3mm x 3mm

• High-Efficiency Microcontroller for Wearable Devices
  • Internal Oscillator Operates up to 96MHz
  • 256KB Flash Memory
  • 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode
  • 16KB Instruction Cache
  • Memory Protection Unit (MPU)
  • Low 1.1V VCORE Supply Voltage
  • 3.6V GPIO Operating Range
  • Internal LDO Provides Operation from Single Supply
  • Wide Operating Temperature: -40°C to +105°C
• Power Management Maximizes Uptime for Battery Applications
  • 85μA/MHz Active Executing from Flash
  • 2μA Full Memory Retention Power in Backup Mode at VDD = 1.8V
  • 450nA Ultra-Low Power RTC at VDD = 1.8V
  • Internal 80kHz Ring Oscillator
• Optimal Peripheral Mix Provides Platform Scalability
  • Up to 14 General-Purpose I/O Pins
  • Up to Two SPI
  • I2S
  • Up to Two UARTs
  • Up to Two I2C, 3.4Mbps High Speed
  • Four-Channel Standard DMA Controller
  • Three 32-Bit Timers
  • Watchdog Timer
  • CMOS-Level 32.768kHz RTC Output

Ordering Information appears at end of data sheet.

Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

19-100236; Rev 9; 6/22

• Sports Watches
• Fitness Monitors
• Wearable Medical Patches
• Portable Medical Devices
• Industrial Sensors
• IoT
• Optical Modules: QSFP-DD, QSFP, 400G

Pin Description

• 16 WLP
• POWER
• A3

Pin Description (continued)

• 16 WLP
• A4
• B2
• —
• CLOCK
• A2
• A1
• RESET
• B1
• GENERAL-PURPOSE I/O (See Table 3 and Table 4 for pin mapping.)
• C1
• C2
• D1
• D2
• D3
• D4
• C3
• C4
• B4
• B3
• —
• —
• —
• —

Detailed Description

The MAX32660 is an ultra-low power, cost-effective, highly-integrated microcontroller designed for batterypowered devices and wireless sensors. It combines a flexible and versatile power management unit with the powerful Arm Cortex-M4 processor with FPU. The device enables designs with complex sensor processing without compromising battery life. It also offers legacy designs an easy and cost optimal upgrade path from 8- or 16-bit microcontrollers. The device integrates up to 256KB of flash memory and 96KB of RAM to accommodate application and sensor code.

The device features four powerful and flexible power modes. It can operate from a single- or dual-supply battery voltage, typically provided by a PMIC. The I2C port supports standard, fast, fast-plus, and high-speed modes, operating up to 3400kbps. Two UARTs are provided, and the SPI ports can run up to 48MHz in both controller and target mode. Three general-purpose 32-bit timers, a watchdog timer, and a real-time clock are also provided. An I2S interface provides audio streaming to a codec.

Memory

Internal Flash Memory

256KB of internal flash memory provides nonvolatile storage of program and data memory.

Internal SRAM

The internal 96KB SRAM provides low-power retention of application information in all power modes except shutdown. The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention feature is optional, and is configurable. This granularity allows the application to minimize its power consumption by only retaining the most essential data.

Clocking Scheme

The high-frequency internal oscillator (HFIO) operates at a nominal frequency of 96MHz.

Optionally, two other oscillators can be selected depending upon power needs:

• 80kHz nanoring oscillator
• 32.768kHz oscillator (external crystal required)

This clock is the primary clock source for the digital logic and peripherals.

An external 32.768kHz timebase is required when using the RTC.

Figure 6. System Clocking Diagram

General-Purpose I/O and Special Function Pins

Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function signals associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Though this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical Characteristics tables.

In GPIO mode, each pin of a port has an interrupt function that can be independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs share the same interrupt vector. Some packages do not have all of the GPIOs available.

When configured as GPIOs, the following features are provided. These features can be independently enabled or disabled on a per-pin basis.

• Configurable as input, output, bidirectional, or highimpedance
• Optional internal pullup resistor or internal pulldown resistor when configured as input
• Wake up from low-power modes on rising or falling edge
• Selectable standard- or high-drive modes

The MAX32660 provides up to 14 GPIOs for the 20-pin TQFN and up to 10 GPIOs for the 16-bump WLP.

Standard DMA Controller

The standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral data transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported:

• 4 channel
• Peripheral to data memory
• Data memory to peripheral
• Data memory to data memory
• Event support

All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO.

Power Management

Power Management Unit

The power management unit (PMU) provides high-performance operation while minimizing power consumption. It exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.

The PMU provides the following features:

• User-configurable system clock
• Automatic enabling and disabling of crystal oscillators based on power mode
• Multiple clock domains
• Fast wake-up of powered-down peripherals when activity detected

Active Mode

In this mode, the CPU is executing application code and all digital and analog peripherals are available on demand. Dynamic clocking disables peripherals not in use, providing the optimal mix of high-performance and low-power consumption.

Sleep Mode

This mode allows for low-power consumption operation. The CPU is asleep, peripherals are on and the standard DMA block is available. The GPIO or any active peripheral can be configured to interrupt and cause transition to the Active mode.

Deep-Sleep Mode

This mode corresponds to the Arm Cortex-M4 processor with FPU Deep-sleep mode. In this mode, the register settings and all volatile memory is preserved. The GPIO pins retain their state in this mode. The high-speed oscillator that generates the 96MHz system clock can be shut down to provide additional power savings over Sleep mode.

Multiple system events can cause the device to wake from Deep-sleep mode and return to the Active mode, including:

• RTC alarm
• Enabled GPIO interrupt

Backup Mode

This mode places the CPU in a static, low-power state. In Backup mode, all of the SRAM can be retained. Data retention in this mode is maintained by the VDD supply only. SRAM retention can be 0KB, 16KB, 32KB, 64KB, or full 96KB. Backup mode supports the same wake-up sources as Deep-sleep mode.

Real-Time Clock

A real-time clock (RTC) keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software.

The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to remain in an extremely low-power mode, but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/4096 subsecond alarm can be programmed between 244μs and 12 days. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low power modes.

The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table.

An RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm resolution. Under most circumstances, the oscillator does not require any calibration.

Watchdog Timer

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One of the most effective countermeasures is the watchdog timer (WDT), which detects runaway code or system unresponsiveness.

The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt, system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction execution.

The MAX32660 provides one instance of the watchdog timer (WDT0).

Programmable Timers

General-purpose, 32-bit timers provide timing, capture/ compare, or generation of pulse-width modulated (PWM) signals with minimal software interaction.

The timer provides the following features:

• 32-bit up/down autoreload
• Programmable prescaler
• PWM output generation
• Capture, compare, and capture/compare capability
• External pin multiplexed with GPIO for timer input, clock gating, or capture
• Timer output pin
• Timer interrupt

The MAX32660 provides three 32-bit timers: TMR0, TMR1, and TMR2.

I/O functionality is supported for TMR0 only (P0.3, Alternate Function 3). Note that the function of a port can be multiplexed with other functions on the GPIO pins, so it might not be possible to use all the ports depending on the device configuration.

Figure 7. 32-Bit Timer

Serial Peripherals

I2C Interface

The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many or many-tomany communications medium. These engines support Standard-mode, Fast-mode, Fast-mode Plus and Highspeed mode I2C speeds. It provides the following features:

• Controller or target mode operation
  • Supports up to 4 different target addresses in target mode
• Supports standard 7-bit addressing or 10-bit addressing
• RESTART condition
• Interactive receive mode
• Transmit FIFO preloading
• Support for clock stretching to allow slower target devices to operate on higher speed busses
• Multiple transfer rates
  • Standard-mode: 100kbps
  • Fast-mode: 400kbps
  • Fast-mode Plus: 1000kbps
  • High-speed mode: 3400kbps
• Internal filter to reject noise spikes
• Receive FIFO depth of 8 bytes
• Transmit FIFO depth of 8 bytes

The MAX32660 provides two instances of the I2C peripheral (I2C0 and I2C1).

Serial Peripheral Interface

The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface between multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals, and one or more target select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.

The provided SPI peripherals can operate in either target or controller mode and provide the following features:

• SPI modes 0, 1, 2, 3 for single-bit communication
• 3- or 4-wire mode for single-bit target device communication
• Full-duplex operation in single-bit, 4-wire mode
• Multicontroller mode fault detection
• Programmable interface timing
• Programmable SCK frequency and duty cycle
• 32-byte transmit and receive FIFOs
• Target select assertion and deassertion timing with respect to leading/trailing SCK edge

The MAX32660 provides two instances of this SPI peripheral (SPI0, SPI1) with the following specifications (Table 1):

Table 1. SPI Configuration Options

I2S Interface

The I2S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I2S Bus Specification, June 5, 1996. It provides the following features:

• Target mode operation
• Normal and left-justified data alignment
• 16-bit audio transfer
• Wake-up on FIFO status (full/empty/threshold)
• Interrupts generated for FIFO status
• Receiver FIFO depth of 32 bytes
• Transmitter FIFO depth of 32 bytes

The MAX32660 provides one instance of the I2S peripheral that is multiplexed with the SPI1 peripheral.

UART

The universal asynchronous receiver-transmitter (UART) interface supports asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry standard request to send (RTS) and clear to send (CTS) flow control signaling. Each UART is individually programmable.

• 2-wire interface or 4-wire interface with flow control
• 8-byte send/receive FIFO
• Full-duplex operation for asynchronous data transfers
• Interrupts available for frame error, parity error, CTS, Rx FIFO overrun and FIFO full/partially full conditions
• Automatic parity and frame error detection
• Independent baud-rate generator
• Programmable 9th bit parity support
• Multidrop support
• Start/stop bit support
• Hardware flow control using RTS/CTS
• Two DMA channels can be connected (read and write FIFOs)
• Programmable word size (5 bits to 8 bits)

The MAX32660 provides two instances of the UART peripheral (UART0 and UART1) with the specifications shown in Table 2.

Table 2. UART Configuration Options

Bootloader

Some versions of the device contain a small bootloader that resides in flash, providing the ability to update the application code by a host microcontroller. The bootloader can be accessed through the I2C, SPI, or UART interface. These interfaces provide the data channel and the control channel for communicating between the host microcontroller and the MAX32660. The bootloader application load mode is enabled and disabled by either a serial command or hardware connectivity. The serial command is interpreted by the application, which configures the device to enter the bootloader mode. When using the hardware connectivity option, a single GPIO pin and the RSTN pin on the MAX32660 can be configured to allow the MAX32660 to enter the bootloader mode. Refer to Application Note 6471: MAX32660 Bootloader User Guide for details of the bootloader operation and reserved memory locations.

Debug and Development Interface (SWD)

The serial wire debug interface is used for code loading and ICE debug activities. All devices in mass production have the debugging/development interface enabled.

Additional Documentation and Technical Support

Designers must have the following documents to use all the features of this device:

• This data sheet, which contains electrical/timing specifications, package information, and pin descriptions
• The corresponding revision-specific errata sheet
• The corresponding user guide, which contains detailed information and programming guidelines for core features and peripherals

Applications Information

Table 3. GPIO and Alternate Function Matrix, 16 WLP

**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.

†These pins support I2S functionality. Refer to the User Guide for details.

Table 4. GPIO and Alternate Function Matrix, 20 TQFN and 24 TQFN

Typical Application Circuit

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel. Full reel.

Revision History

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

• VCORE-0.3V to +1.21V
• VDD-0.3V to +3.63V
• 32KIN, 32KOUT-0.3V to VDD + 0.3V
• RSTN, All GPIO except P0.[4–7, 9] -0.3V to VDD + 0.3V
• GPIO P0.[4–7, 9]-0.3V to VDD + 0.3V
• Total Current into All GPIO Combined (sink)10

Note: Long-term storage at +150°C is not recommended as this will reduce the lifetime of the flash storage. Please keep long-term storage of the part below +125°C.

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

16 WLP

20 TQFN-EP

24 TQFN-EP

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics