LAN8720AI-CP-TR
Ethernet TransceiverThe LAN8720AI-CP-TR is a ethernet transceiver from Microchip Technology. View the full LAN8720AI-CP-TR datasheet below including absolute maximum ratings.
Manufacturer
Microchip Technology
Category
Ethernet Transceiver
Package
QFN-24-EP(4x4)
Overview
Part: LAN8720A/LAN8720Ai — Microchip Type: 10/100 Ethernet Transceiver Description: Low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O voltage, compliant with IEEE 802.3-2005 standards, supporting RMII interface and HP Auto-MDIX.
Operating Conditions:
- Supply voltage: May be used with a single 3.3V supply (VDD2A, VDD1A). Variable I/O voltage range: +1.6V to +3.6V (VDDIO).
- Operating temperature: 0°C to +85°C (extended commercial), -40°C to +85°C (industrial)
- Clock input: 25 MHz crystal
Absolute Maximum Ratings:
- Latch-Up Performance: Exceeds 150mA per EIA/JESD 78, Class II
Key Specs:
- Ethernet Standards: IEEE 802.3/802.3u (Fast Ethernet), ISO 802-3/IEEE 802.3 (10BASE-T)
- Data Rates: 10 Mbps (10BASE-T), 100 Mbps (100BASE-TX)
- Interface: Reduced Media Independent Interface (RMII)
- I/O Voltage Range (VDDIO): +1.6V to +3.6V
- Internal Regulator: Integrated 1.2V regulator (can be disabled)
- Crystal Frequency: 25 MHz
- RBIAS Resistor: 12.1 kΩ (1%) to ground
Features:
- Auto-negotiation
- Automatic polarity detection and correction (HP Auto-MDIX)
- Link status change wake-up detection
- Various low power modes
- Integrated power-on reset circuit
- Two status LED outputs
- Supports vendor specific register functions
Applications:
- Set-Top Boxes
- Networked Printers and Servers
- Test Instrumentation
- LAN on Motherboard
- Embedded Telecom Applications
- Video Record/Playback Systems
- Cable Modems/Routers
- DSL Modems/Routers
- Digital Video Recorders
- IP and Video Phones
- Wireless Access Points
- Digital Televisions
- Digital Media Adapters/Servers
- Gaming Consoles
- POE Applications
Package:
- 24-pin QFN/SQFN (4x4 mm) Lead-Free RoHS Compliant
Applications
- Set-Top Boxes
- Networked Printers and Servers
- Test Instrumentation
- LAN on Motherboard
- Embedded Telecom Applications
- Video Record/Playback Systems
- Cable Modems/Routers
- DSL Modems/Routers
- Digital Video Recorders
- IP and Video Phones
- Wireless Access Points
- Digital Televisions
- Digital Media Adapters/Servers
- Gaming Consoles
- POE Applications (Refer to Application Note 17.18)
Pin Configuration
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
- Note 2-1 When a lower case 'n' is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low.
- Note 2-2 The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2.
TABLE 2-1: RMII SIGNALS
| Num Pins | Name | Symbol | Buffer Type | Description |
|---|---|---|---|---|
| 1 | Transmit Data 0 | TXD0 | VIS | The MAC transmits data to the transceiver using this signal. |
| 1 | Transmit Data 1 | TXD1 | VIS | The MAC transmits data to the transceiver using this signal. |
| 1 | Transmit Enable | TXEN | VIS (PD) | Indicates that valid transmission data is present on TXD[1:0]. |
| 1 | Receive Data 0 | RXD0 | VO8 | Bit 0 of the 2 data bits that are sent by the trans - ceiver on the receive path. |
| 1 | PHY Operat - ing Mode 0 Configuration Strap | MODE0 | VIS (PU) | Combined with MODE1 and MODE2, this config - uration strap sets the default PHY mode. See Note 2-3 for more information on configura - tion straps. Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 27 for additional details. |
| 1 | Receive Data 1 | RXD1 | VO8 | Bit 1 of the 2 data bits that are sent by the trans - ceiver on the receive path. |
| 1 | PHY Operat - ing Mode 1 Configuration Strap | MODE1 | VIS (PU) | Combined with MODE0 and MODE2, this config - uration strap sets the default PHY mode. See Note 2-3 for more information on configura - tion straps. Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 27 for additional details. |
| 1 | Receive Error | RXER | VO8 | This signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver. |
| 1 | PHYAddress 0 Configuration Strap | PHYAD0 | VIS (PD) | This configuration strap sets the transceiver's SMI address. See Note 2-3 for more information on configura - tion straps. Note: Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 26 for additional information. |
Absolute Maximum Ratings
| Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5-1) ............................................................................... | -0.5V to +3.6V |
|---|---|
| Digital Core Supply Voltage (VDDCR) (Note 5-1)...................................................................................... | -0.5V to +1.5V |
| Ethernet Magnetics Supply Voltage ........................................................................................................... -0.5V | to +3.6V |
| Positive voltage on signal pins, with respect to ground (Note 5-2) .............................................................................+6V | |
| Negative voltage on signal pins, with respect to ground (Note 5-3)..........................................................................-0.5V | |
| Positive voltage on XTAL1/CLKIN, with respect to ground ......................................................................................+3.6V | |
| Positive voltage on XTAL2, with respect to ground..................................................................................................+2.5V | |
| Ambient Operating Temperature in Still Air (T A )............................................................................................... | Note 5-40 |
| Storage Temperature ..............................................................................................................................-55 o C to | +150 o C |
| Lead Temperature Range ...........................................................................................Refer to JEDEC Spec. | J-STD-020 |
| HBM ESD Performance per JEDEC JESD22-A114............................................................................................Class | 3A |
| IEC61000-4-2 Contact Discharge ESD Performance (Note 5-5)............................................................................+/-8kV | |
| IEC61000-4-2 Air-Gap Discharge ESD Performance (Note 5-5) ..........................................................................+/-15kV | |
| Latch-up Performance per EIA/JESD 78 ...........................................................................................................+/-150mA |
- Note 5-2 This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.
- Note 5-3 This rating does not apply to the following pins: RBIAS.
- Note 5-4 0 o C to +85 o C for extended commercial version, -40 o C to +85 o C for industrial version.
- Note 5-5 Performed by independent 3rd party test facility.
Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 5.2, "Operating Conditions*", Section 5.1, "Absolute Maximum Ratings*", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified otherwise.
Thermal Information
| Parameter | Symbol | Value | Units | Notes |
|---|---|---|---|---|
| Junction-to-Ambient | JA | 58 | °C/W | 0 Meters/second |
| JA | 51 45 | °C/W | 1 Meters/second | |
| JA | °C/W | 2.5 Meters/second | ||
| Junction-to-Top-of-Package | JT | 1.1 | °C/W | 0 Meters/second |
| Junction-to-Board | JB | 36 | °C/W | |
| Junction-to-Case | JC | 11.3 | °C/W |
Typical Application
This section provides typical application diagrams for the following:
- Simplified System Level Application Diagram
- Power Supply Diagram (1.2V Supplied by Internal Regulator)
- Power Supply Diagram (1.2V Supplied by External Source)
- Twisted-Pair Interface Diagram (Single Power Supply)
- Twisted-Pair Interface Diagram (Dual Power Supplies)
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| LAN8720 | Microchip Technology | — |
| LAN8720A | Microchip Technology | — |
| LAN8720A-CP-ABC | Microchip Technology | — |
| LAN8720A-CP-TR | Microchip Technology | 24-pin QFN |
| LAN8720AI | Microchip Technology | — |
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