LAN8720A-CP-TR

Part: LAN8720A/LAN8720AI from Microchip

Type: Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Key Specs:

• LVCMOS Variable I/O voltage range: +1.6V to +3.6V
• Integrated regulator: 1.2V
• Ethernet speeds: 10Mbps (10BASE-T), 100Mbps (100BASE-TX)
• Extended commercial temperature range: 0°C to +85°C
• Industrial temperature range: -40°C to +85°C
• Crystal frequency: 25MHz

Features:

• Single-Chip Ethernet Physical Layer Transceiver (PHY)
• Comprehensive flexPWR® Technology
• Flexible Power Management Architecture
• HP Auto-MDIX support
• Compliant with IEEE802.3/802.3u (Fast Ethernet)
• Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
• Loop-back modes
• Auto-negotiation
• Automatic polarity detection and correction
• Link status change wake-up detection
• Vendor specific register functions
• Supports the reduced pin count RMII interface
• Various low power modes
• Integrated power-on reset circuit
• Two status LED outputs
• Latch-Up Performance Exceeds 150mA per EIA/JESD 78, Class II
• May be used with a single 3.3V supply
• Ability to use a low cost 25Mhz crystal for reduced BOM

Applications:

• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications

Package:

• 24-pin QFN/SQFN: 4 x 4mm

• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications (Refer to Application Note 17.18)

Key Benefits

• High-Performance 10/100 Ethernet Transceiver
• Compliant with IEEE802.3/802.3u (Fast Ethernet)
• Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
• Loop-back modes
• Auto-negotiation
• Automatic polarity detection and correction
• Link status change wake-up detection
• Vendor specific register functions
• Supports the reduced pin count RMII interface
• Power and I/Os
  • Various low power modes
  • Integrated power-on reset circuit
  • Two status LED outputs
  • Latch-Up Performance Exceeds 150mA per EIA/JESD 78, Class II
  • May be used with a single 3.3V supply
• Additional Features
  • Ability to use a low cost 25Mhz crystal for reduced BOM
• Packaging
  • 24-pin QFN/SQFN (4x4 mm) Lead-Free RoHS Compliant package with RMII
• Environmental
  • Extended commercial temperature range (0°C to +85°C)
  • Industrial temperature range version available (-40°C to +85°C)

NOTE: Exposed pad (VSS) on bottom of package must be connected to ground

• Note 2-1 When a lower case "n" is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low.
• Note 2-2 The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2.

Num Pins	Name	Symbol	Buffer Type	Description
1	Transmit Data 0	TXD0	VIS	The MAC transmits data to the transceiver using this signal.
1	Transmit Data 1	TXD1	VIS	The MAC transmits data to the transceiver using this signal.
1	Transmit Enable	TXEN	VIS (PD)	Indicates that valid transmission data is present on TXD[1:0].
1	Receive Data 0	RXD0	VO8	Bit 0 of the 2 data bits that are sent by the trans ceiver on the receive path.
	PHY Operat ing Mode 0 Configuration Strap	MODE0	VIS (PU)	Combined with MODE1 and MODE2, this config uration strap sets the default PHY mode. See Note 2-3 for more information on configura tion straps. Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 27 for additional details.
1	Receive Data 1	RXD1	VO8	Bit 1 of the 2 data bits that are sent by the trans ceiver on the receive path.
	PHY Operat ing Mode 1 Configuration Strap	MODE1	VIS (PU)	Combined with MODE0 and MODE2, this config uration strap sets the default PHY mode. See Note 2-3 for more information on configura tion straps. Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 27 for additional details.
1	Receive Error	RXER	VO8	This signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver.
	PHY Address 0 Configuration Strap	PHYAD0	VIS (PD)	This configuration strap sets the transceiver's SMI address. See Note 2-3 for more information on configura tion straps. Note: Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 26 for additional information.

TABLE 2-1: RMII SIGNALS

TABLE 2-1: RMII SIGNALS (CONTINUED)

Num Pins	Name	Symbol	Buffer Type	Description
11	Carrier Sense / Receive Data Valid	CRS_DV	VO8	This signal is asserted to indicate the receive medium is non-idle. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte (10101011) is received. Note: Per the RMII standard, transmitted data is not looped back onto the receive data pins in 10BASE-T half-duplex mode.
11	PHY Operat ing Mode 2 Configuration Strap	MODE2	VIS (PU)	Combined with MODE0 and MODE1, this config uration strap sets the default PHY mode. See Note 2-3 for more information on configura tion straps. Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 27 for additional details.

Note 2-3 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 26 for additional information.

NUM PINS	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
	LED 1	LED1	O12	Link activity LED Indication. This pin is driven active when a valid link is detected and blinks when activity is detected. Note: Refer to Section 3.8.1, "LEDs," on page 31 for additional LED information.
1	Regulator Off Configuration Strap	REGOFF	IS (PD)	This configuration strap is used to disable the internal 1.2V regulator. When the regulator is dis abled, external 1.2V must be supplied to VDDCR. • When REGOFF is pulled high to VDD2A with an external resistor, the internal regulator is disabled. • When REGOFF is floating or pulled low, the internal regulator is enabled (default). See Note 2-4 for more information on configura tion straps. Refer to Section 3.7.3, "REGOFF: Note: Internal +1.2V Regulator Configuration," on page 28 for additional details.

TABLE 2-2: LED PINS

NUM PINS	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION

TABLE 2-2: LED PINS (CONTINUED)

Note 2-4 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 26 for additional information.

TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
1	SMI Data Input/Output	MDIO	VIS/ VOD8	Serial Management Interface data input/output
1	SMI Clock	MDC	VIS	Serial Management Interface clock

TABLE 2-4: ETHERNET PINS

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
1	Ethernet TX/ RX Positive Channel 1	TXP	AIO	Transmit/Receive Positive Channel 1
1	Ethernet TX/ RX Negative Channel 1	TXN	AIO	Transmit/Receive Negative Channel 1

TABLE 2-4:	ETHERNET PINS (CONTINUED)
------------	---------------------------

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
1	Ethernet TX/ RX Positive Channel 1	TXP	AIO	Transmit/Receive Positive Channel 1
1	Ethernet TX/ RX Negative Channel 1	TXN	AIO	Transmit/Receive Negative Channel 1

TABLE 2-5: MISCELLANEOUS PINS

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
	LED 2	LED2	O12	Link Speed LED Indication. This pin is driven active when the operating speed is 100Mbps. It is inactive when the operating speed is 10Mbps or during link isolation. Note: Refer to Section 3.8.1, "LEDs," on page 31 for additional LED information.
1	nINT/ REFCLKO Function Select Configuration Strap	nINTSEL	IS (PU)	This configuration strap selects the mode of the nINT/REFCLKO pin. • When nINTSEL is floated or pulled to VDD2A, nINT is selected for operation on the nINT/REFCLKO pin (default). • When nINTSEL is pulled low to VSS, REF- CLKO is selected for operation on the nINT/ REFCLKO pin. See Note 2-4 for more information on configura- tion straps. Note: Refer to See Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection," on page 32 for additional information.

TABLE 2-6: ANALOG REFERENCE PINS

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
	LED 2	LED2	O12	Link Speed LED Indication. This pin is driven active when the operating speed is 100Mbps. It is inactive when the operating speed is 10Mbps or during link isolation. Note: Refer to Section 3.8.1, "LEDs," on page 31 for additional LED information.
1	nINT/ REFCLKO Function Select Configuration Strap	nINTSEL	IS (PU)	This configuration strap selects the mode of the nINT/REFCLKO pin. • When nINTSEL is floated or pulled to VDD2A

TABLE 2-7: POWER PINS

Num PINs	NAME	SYMBOL	BUFFER TYPE	DESCRIPTION
	LED 2	LED2	O12	Link Speed LED Indication. This pin is driven active when the operating speed is 100Mbps. It is inactive when the operating speed is 10Mbps or during link isolation. Note: Refer to Section 3.8.1, "LEDs," on page 31 for additional LED information.
1	nINT/ REFCLKO Function Select Configuration Strap	nINTSEL	IS (PU)	This configuration strap selects the mode of the nINT/REFCLKO pin. • When nINTSEL is floated or pulled to VDD2A, nINT is selected for operation on the nINT/REFCLKO pin (default). • When nINTSEL is pulled low to VSS, REF- CLKO is selected for operation on the nINT/ REFCLKO pin. See Note 2-4 for more information on configura- tion straps. Note: Refer to See Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection," on page 32 for additional information.
1	SMI Data Input/Output	MDIO	VIS/ VOD8	Serial Management Interface data input/output
1	SMI Clock	MDC	VIS	Serial Management Interface clock
1	Ethernet TX/ RX Positive Channel 1	TXP	AIO	Transmit/Receive Positive Channel 1
1	Ethernet TX/ RX Negative Channel 1	TXN	AIO	Transmit/Receive Negative Channel 1

• Digital Core Supply Voltage (VDDCR) (Note 5-1) -0.5V to +1.5V

• Ethernet Magnetics Supply Voltage -0.5V to +3.6V

• Positive voltage on signal pins, with respect to ground (Note 5-2) +6V

• Negative voltage on signal pins, with respect to ground (Note 5-3)-0.5V

• Positive voltage on XTAL1/CLKIN, with respect to ground +3.6V

• Positive voltage on XTAL2, with respect to ground+2.5V

• Ambient Operating Temperature in Still Air (TA) Note 5-40

• Storage Temperature -55°C to +150°C

• Lead Temperature Range Refer to JEDEC Spec. J-STD-020

• HBM ESD Performance per JEDEC JESD22-A114Class 3A

• IEC61000-4-2 Contact Discharge ESD Performance (Note 5-5)+/-8kV

• IEC61000-4-2 Air-Gap Discharge ESD Performance (Note 5-5) +/-15kV

• Latch-up Performance per EIA/JESD 78 +/-150mA

• Note 5-1 When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

• Note 5-2 This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.

• Note 5-3 This rating does not apply to the following pins: RBIAS.

• Note 5-4 0°C to +85°C for extended commercial version, -40°C to +85°C for industrial version.

• Note 5-5 Performed by independent 3rd party test facility.

*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 5.2, "Operating Conditions\\", Section 5.1, "Absolute Maximum Ratings\*", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified otherwise.

TABLE 5-1:	PACKAGE THERMAL PARAMETERS (24-QFN/SQFN)
------------	------------------------------------------

Parameter	Symbol	Value	Units	Notes
Junction-to-Ambient	JA	58 51 45	°C/W	0 Meters/second 1 Meters/second 2.5 Meters/second
Junction-to-Top-of-Package	JT	1.1	°C/W	0 Meters/second
Junction-to-Board	JB	36	°C/W
Junction-to-Case	JC	11.3	°C/W

5.4 Power Consumption

This section details the device power measurements taken over various operating conditions. Unless otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, Power-Down Modes for a description of the power down modes. For more information on the REF_- CLK modes, see Section 3.7.4, nINTSEL: nINT/REFCLKO Configuration.

5.4.1 REF_CLK IN MODE

TABLE 5-2: DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK IN MODE)

Power Pin Group		VDDA3.3 Power PinS(mA)	VDDCR Power pin(mA)	VDDIO power pin(mA)	Total Current (mA)	Total Power (mW)
	Max	28	21	0.6	49	159
100BASE-TX /w traffic	Typical	26	19	0.5	45	148
	Min	23	18	0.3	41	96 Note 5-8
	Max	9.7	13	0.6	24	77
10BASE-T /w traffic	Typical	8.9	12	0.5	22	70
	Min	8.3	12	0.3	20	42 Note 5-8
Energy Detect Power Down	Max	4.2	3.0	0.2	7.4	25
	Typical	4.1	1.9	0.2	6.2	21
	Min	3.9	1.9	0	5.8	16 Note 5-8
General Power Down	Max	0.4	2.8	0.2	3.4	11.2
	Typical	0.3	1.8	0.2	2.3	7.6
	Min	0.3	1.7	0	2	3.0 Note 5-8

• Note 5-6 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
• Note 5-7 Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
• Note 5-8 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.

5.4.2 REF_CLK OUT MODE

. TABLE 5-3: DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK OUT MODE)

Power Pin Group		VDDA3.3 Power Pins(mA)	VDDCR Power Pin(mA)	VDDIO Power Pin(mA)	Total Current (mA)	Total Power (mW)
	Max	28	20	6.3	54	179
100BASE-T /w traffic	Typical	26	19	5.8	50	164
	Min	22	15	2.9	39	93 Note 5-11
	Max	9.9	13	6.4	30	96
10BASE-T /w traffic	Typical	8.8	12	5.6	26	85
	Min	7.1	10	3.0	20	41 Note 5-11
Energy Detect Power Down	Max	4.5	2.7	0.3	7.5	25
	Typical	4.0	1.5	0.2	5.7	19
	Min	3.9	1.2	0	5.1	15 Note 5-11
General Power Down	Max	0.4	2.5	0.2	3.1	10.2
	Typical	0.4	1.3	0.2	1.9	6.3
	Min	0.4	1.0	0	1.4	2.5 Note 5-11

Note 5-9 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled.

Note 5-10 Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.

Note 5-11 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.