LAN8720A-CP-ABC

Part: Microchip LAN8720A/LAN8720Ai

Type: Ethernet Physical Layer Transceiver (PHY)

Description: Low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O voltage, compliant with IEEE 802.3-2005 standards, supporting RMII interface and HP Auto-MDIX.

Operating Conditions:

• Supply voltage: 3.3V (single supply option); I/O voltage range: +1.6V to +3.6V
• Operating temperature: 0 to +85 °C (extended commercial) or -40 to +85 °C (industrial)
• Data rates: 10 Mbps (10BASE-T) and 100 Mbps (100BASE-TX)

Absolute Maximum Ratings:

• Max supply voltage: null
• Max continuous current: null
• Max junction/storage temperature: null

Key Specs:

• Data Rates: 10 Mbps (10BASE-T) and 100 Mbps (100BASE-TX)
• Interface: Reduced Media Independent Interface (RMII)
• I/O Voltage Range: +1.6V to +3.6V
• Supply Voltage: Single 3.3V supply operation possible
• Integrated Regulator: 1.2V linear regulator
• Crystal Frequency: 25 MHz
• Compliance: IEEE 802.3-2005 standards
• Features: HP Auto-MDIX, Auto-negotiation

Features:

• Single-Chip Ethernet Physical Layer Transceiver (PHY)
• Comprehensive flexPWR® Technology
• HP Auto-MDIX support
• Compliant with IEEE802.3/802.3u (Fast Ethernet) and ISO 802-3/IEEE 802.3 (10BASE-T)
• Loop-back modes, Auto-negotiation, Automatic polarity detection and correction
• Link status change wake-up detection
• Various low power modes
• Integrated power-on reset circuit
• Two status LED outputs
• Ability to use a low cost 25Mhz crystal

Applications:

• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications

Package:

• 24-pin QFN/SQFN (4x4 mm)

• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications (Refer to Application Note 17.18)

FIGURE 2-1: 24-QFN/SQFN PIN ASSIGNMENTS (TOP VIEW)

NOTE: Exposed pad (VSS) on bottom of package must be connected to ground

• Note 2-1 When a lower case "n" is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low.
• Note 2-2 The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2.

TABLE 2-1: RMII SIGNALS

TABLE 2-1: RMII SIGNALS (CONTINUED)

Note 2-3 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 26 for additional information.

TABLE 2-2: LED PINS

TABLE 2-2: LED PINS (CONTINUED)

Note 2-4 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 26 for additional information.

TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS

TABLE 2-4: ETHERNET PINS

TABLE 2-4: ETHERNET PINS (CONTINUED)

TABLE 2-5: MISCELLANEOUS PINS

TABLE 2-6: ANALOG REFERENCE PINS

TABLE 2-7: POWER PINS

5.2 Operating Conditions**

are NOT 5 volt tolerant unless specified otherwise.

• Analog Port Supply Voltage (VDD1A, VDD2A) +3.0V to +3.6V
• Digital Core Supply Voltage (VDDCR) +1.08V to +1.32V
• Ethernet Magnetics Supply Voltage +2.25V to +3.6V
• Ambient Operating Temperature in Still Air (TA) Note 5-4

^**Proper operation of the device is guaranteed only within the ranges specified in this section. After the device has completed power-up, VDDIO and the magnetics power supply must maintain their voltage level with +/-10%. Varying the voltage greater than +/-10% after the device has completed power-up can cause errors in device operation.

Note: Do not drive input signals without power supplied to the device.

^*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 5.2, "Operating Conditions\\", Section 5.1, "Absolute Maximum Ratings\*", or any other applicable section of this specification is not implied. Note, device signals

TABLE 5-1: PACKAGE THERMAL PARAMETERS (24-QFN/SQFN)

5.4 Power Consumption

This section details the device power measurements taken over various operating conditions. Unless otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, Power-Down Modes for a description of the power down modes. For more information on the REF_- CLK modes, see Section 3.7.4, nINTSEL: nINT/REFCLKO Configuration.

5.4.1 REF_CLK IN MODE

TABLE 5-2: DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK IN MODE)

• Note 5-6 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
• Note 5-7 Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
• Note 5-8 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.

5.4.2 REF_CLK OUT MODE

TABLE 5-3: DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK OUT MODE)

• Note 5-9 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
• Note 5-10 Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
• Note 5-11 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.

5.5 DC Specifications

TABLE 5-4: details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage operation. TABLE 5-5: details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8V, 2.5V, and 3.3V VDDIO cases.

TABLE 5-4: NON-VARIABLE I/O BUFFER CHARACTERISTICS

Note 5-13 XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.

TABLE 5-5: VARIABLE I/O BUFFER CHARACTERISTICS

Note 5-14 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical).

TABLE 5-6: 100BASE-TX TRANSCEIVER CHARACTERISTICS

Note 5-15 Measured at line side of transformer, line replaced by 100 (+/- 1%) resistor.

Note 5-16 Offset from 16nS pulse width at 50% of pulse peak.

Note 5-17 Measured differentially.

TABLE 5-7: 10BASE-T TRANSCEIVER CHARACTERISTICS

Note 5-18 Min/max voltages guaranteed as measured with 100 resistive load.

5.6 AC Specifications

This section details the various AC timing specifications of the device.

Note 5-19 The SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for additional timing information.

Note 5-20 The RMII timing adheres to the RMII Consortium RMII Specification R1.2.

5.6.1 EQUIVALENT TEST LOAD

Output timing specifications assume a 25pF equivalent test load, unless otherwise noted, as illustrated in Figure 5-1 below.

FIGURE 5-1: OUTPUT EQUIVALENT TEST LOAD

5.6.2 POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power supplies can turn on in any order provided they all reach operational levels within the specified time period tpon. Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period poff.

FIGURE 5-2: POWER SEQUENCE TIMING

TABLE 5-8: POWER SEQUENCE TIMING VALUES

Note: When the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and the 3.3V power supply. For additional information refer to Section 3.7.3, REGOFF: Internal +1.2V Regulator Configuration.

5.6.3 POWER-ON NRST & CONFIGURATION STRAP TIMING

This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must not be deasserted before tpurstd after all external power supplies have reached 80% of their nominal operating levels. In order for valid configuration strap values to be read at power-up, the tcss and tcsh timing constraints must be followed. Refer to Section 3.8.5, Resets for additional information.

FIGURE 5-3: POWER-ON NRST & CONFIGURATION STRAP TIMING

TABLE 5-9: POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES

Note 5-21 nRST deassertion must be monotonic.

Note 5-22 Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7, Configuration Straps for details. Configuration straps must only be pulled high or low and must not be driven as inputs.

Note 5-23 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.

5.6.4 RMII INTERFACE TIMING

5.6.4.1 RMII Timing (REF_CLK Out Mode)

The 50MHz REF_CLK OUT timing applies to the case when nINTSEL is pulled-low. In this mode, a 25MHz crystal or clock oscillator must be input on the XTAL1/CLKIN and XTAL2 pins. For more information on REF_CLK Out Mode, see Section 3.7.4.2, REF\_CLK Out Mode.

FIGURE 5-4: RMII TIMING (REF_CLK OUT MODE)

TABLE 5-10: RMII TIMING VALUES (REF_CLK OUT MODE)

Note 5-24 Timing was designed for system load between 10 pf and 25 pf.

5.6.4.2 RMII Timing (REF_CLK In Mode)

The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high. In this mode, a 50MHz clock must be input on the CLKIN pin. For more information on REF_CLK In Mode, see Section 3.7.4.1, REF\_CLK In Mode.

FIGURE 5-5: RMII TIMING (REF_CLK IN MODE)

TABLE 5-11: RMII TIMING VALUES (REF_CLK IN MODE)

Note 5-25 Timing was designed for system load between 10 pf and 25 pf.

5.6.4.3 RMII CLKIN Requirements

TABLE 5-12: RMII CLKIN (REF_CLK) TIMING VALUES

5.6.5 SMI TIMING

This section specifies the SMI timing of the device. Please refer to Section 3.5, Serial Management Interface (SMI) for additional details.

FIGURE 5-6: SMI TIMING

TABLE 5-13: SMI TIMING VALUES

5.7 Clock Circuit

The device can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTAL1/XTAL2). Either a 300uW or 100uW 25MHz crystal may be utilized. The 300uW 25MHz crystal specifications are detailed in Section 5.7.1, "300uW 25MHz Crystal Specification," on page 63. The 100uW 25MHz crystal specifications are detailed in Section 5.7.2, "100uW 25MHz Crystal Specification," on page 64.

5.7.1 300UW 25MHZ CRYSTAL SPECIFICATION

When utilizing a 300uW 25MHz crystal, the following circuit design (Figure 5-7) and specifications (Table 5-14) are required to ensure proper operation.

FIGURE 5-7: 300UW 25MHZ CRYSTAL CIRCUIT

TABLE 5-14: 300UW 25MHZ CRYSTAL SPECIFICATIONS

5.7.2 100UW 25MHZ CRYSTAL SPECIFICATION

When utilizing a 100uW 25MHz crystal, the following circuit design (Figure 5-8) and specifications (Table 5-15) are required to ensure proper operation.

FIGURE 5-8: 100UW 25MHZ CRYSTAL CIRCUIT

TABLE 5-15: 100UW 25MHZ CRYSTAL SPECIFICATIONS

TABLE 5-15: 100UW 25MHZ CRYSTAL SPECIFICATIONS (CONTINUED)

• Note 5-31 The maximum allowable values for Frequency Tolerance and Frequency Stability are application dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the combination of these two values must be approximately ±45 PPM (allowing for aging).
• Note 5-32 Frequency Deviation Over Time is also referred to as Aging.
• Note 5-33 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as ±100 PPM.
• Note 5-34 The crystal must support 100uW operation to utilize this circuit.
• Note 5-35 0°C for extended commercial version, -40°C for industrial version.
• Note 5-36 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. The total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 MHz.

This section provides typical application diagrams for the following:

• Simplified System Level Application Diagram
• Power Supply Diagram (1.2V Supplied by Internal Regulator)
• Power Supply Diagram (1.2V Supplied by External Source)
• Twisted-Pair Interface Diagram (Single Power Supply)
• Twisted-Pair Interface Diagram (Dual Power Supplies)

3.9.1 SIMPLIFIED SYSTEM LEVEL APPLICATION DIAGRAM