IR2110STRPBF
The IR2110STRPBF is an electronic component. View the full IR2110STRPBF datasheet below including electrical characteristics, absolute maximum ratings.
Overview
Part: IR2110/IR2113
Type: High voltage, high speed power MOSFET and IGBT drivers
Description: High voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels, fully operational to +500V or +600V, featuring 2A/2A output current and 120 ns typical turn-on delay.
Operating Conditions:
- Supply voltage (VCC, VB): 10–20 V
- Logic supply voltage (VDD): VSS + 3V to VSS + 20V
- Operating temperature: -40 to 125 °C
- High side floating supply offset voltage (VS): Note 1 to 500V (IR2110), Note 1 to 600V (IR2113)
Absolute Maximum Ratings:
- Max high side floating supply voltage (VB): 525 V (IR2110), 625 V (IR2113)
- Max low side fixed supply voltage (VCC): 25 V
- Max logic supply voltage (VDD): VSS + 25 V
- Max junction temperature: 150 °C
- Max storage temperature: -55 to 150 °C
- Allowable offset supply voltage transient (dVs/dt): 50 V/ns
Key Specs:
- Turn-on propagation delay (ton): 120 ns (typ) at VS = 0V
- Turn-off propagation delay (toff): 94 ns (typ) at VS = 500V/600V
- Delay matching, HS & LS (IR2110): 10 ns (max)
- Output high short circuit pulsed current (IO+): 2.0 A (min)
- Output low short circuit pulsed current (IO-): 2.0 A (min)
- Quiescent VBS supply current (IQBS): 125 μA (typ) at VIN = 0V or VDD
- Quiescent VCC supply current (IQCC): 180 μA (typ) at VIN = 0V or VDD
- Logic '1' input voltage (VIH): 9.5 V (min)
Features:
- Gate drive supply range from 10 to 20V
- Floating channel designed for bootstrap operation, fully operational to +500V or +600V
- Tolerant to negative transient voltage, dV/dt immune
- Undervoltage lockout for both channels
- CMOS Schmitt-triggered inputs with pull-down
- 3.3V logic compatible, separate logic supply range from 3.3V to 20V
- Cycle by cycle edge-triggered shutdown logic
- Outputs in phase with inputs
- Matched propagation delay for both channels
Package:
- 14-Lead PDIP
- 16-Lead SOIC
Electrical Characteristics
VBIAS (V CC , V BS , V DD ) = 15V, C L = 1000 pF, T A = 25 ° C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.
| Symbol | Definition | Figure | Min. | Typ. | Max. | Units | Test Conditions |
|---|---|---|---|---|---|---|---|
| t on | Turn-on propagation delay | 7 | - | 120 | 150 | ns | V S = 0V |
| t off | Turn-off propagation delay | 8 | - | 94 | 125 | ns | V S = 500V/600V |
| t sd | Shutdown propagation delay | 9 | - | 110 | 140 | ns | V S = 500V/600V |
| t r | Turn-on rise time | 10 | - | 25 | 35 | ns | |
| t f | Turn-off fall time | 11 | - | 17 | 25 | ns | |
| MT | Delay matching, HS & LS (IR2110) | - | - | - | 10 | ns | |
| MT | turn-on/off (IR2113) | - | - | - | 20 | ns |
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
| Symbol | Definition | Definition | Min. | Max. | Units |
|---|---|---|---|---|---|
| V B | High side floating supply voltage (IR2110) | High side floating supply voltage (IR2110) | -0.3 | 525 | V |
| V B | (IR2113) | (IR2113) | -0.3 | 625 | V |
| V S | High side floating supply offset voltage | High side floating supply offset voltage | V B - 25 | V B + 0.3 | V |
| V HO | High side floating output voltage | High side floating output voltage | V S - 0.3 | V B + 0.3 | V |
| V CC | Low side fixed supply voltage | Low side fixed supply voltage | -0.3 | 25 | V |
| V LO | Low side output voltage | Low side output voltage | -0.3 | V CC + 0.3 | V |
| V DD | Logic supply voltage | Logic supply voltage | -0.3 | V SS + 25 | V |
| V SS | Logic supply offset voltage | Logic supply offset voltage | V CC - 25 | V CC + 0.3 | V |
| V IN | Logic input voltage (HIN, LIN & SD) | Logic input voltage (HIN, LIN & SD) | V SS - 0.3 | V DD + 0.3 | V |
| dV s /dt | Allowable offset supply voltage transient (figure 2) | Allowable offset supply voltage transient (figure 2) | - | 50 | V/ns |
| P D | Package power dissipation@TA ≤ +25 ° C | (14 lead DIP) | - | 1.6 | W |
| P D | (16 lead SOIC) | - | 1.25 | W | |
| R THJA | Thermal resistance, junction to ambient | (14 lead DIP) | - | 75 | ° C/W |
| R THJA | (16 lead SOIC) | - | 100 | ° C/W | |
| T J | Junction temperature | Junction temperature | - | 150 | ° C |
| T S | Storage temperature | Storage temperature | -55 | 150 | ° C |
| T L | Lead temperature (soldering, 10 seconds) | Lead temperature (soldering, 10 seconds) | - | 300 | ° C |
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V S and V SS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 36 and 37.
| Symbol | Definition | Definition | Min. | Max. | Units |
|---|---|---|---|---|---|
| V B | High side floating supply absolute voltage | High side floating supply absolute voltage | V S + 10 | V S + 20 | V |
| V S | High side floating supply offset voltage | (IR2110) | Note 1 | 500 | V |
| V S | (IR2113) | Note 1 | 600 | V | |
| V HO | High side floating output voltage | High side floating output voltage | V S | V B | V |
| V CC | Low side fixed supply voltage | Low side fixed supply voltage | 10 | 20 | V |
| V LO | Low side output voltage | Low side output voltage | 0 | VCC | V |
| V DD | Logic supply voltage | Logic supply voltage | V SS + 3 | V SS + 20 | V |
| V SS | Logic supply offset voltage | Logic supply offset voltage | -5 (Note 2) | 5 | V |
| V IN | Logic input voltage (HIN, LIN & SD) | Logic input voltage (HIN, LIN & SD) | V SS | V DD | V |
| T A | Ambient temperature | Ambient temperature | -40 | 125 | ° C |
Note 1: Logic operational for V S of -4 to +500V. Logic state held for V S of -4V to -V BS . (Please refer to the Design Tip DT97-3 for more details).
Note 2: When VDD < 5V, the minimum VSS offset is limited to -V DD.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| IR2110 | Infineon Technologies | — |
| IR2110-1 | Infineon Technologies | — |
| IR2110-1PBF | Infineon Technologies | — |
| IR2110-2 | Infineon Technologies | — |
| IR2110-2PBF | Infineon Technologies | — |
| IR2110PBF | Infineon Technologies | — |
| IR2110S | Infineon Technologies | — |
| IR2110SPBF | Infineon Technologies | — |
Get structured datasheet data via API
Get started free