IR2110SPBF

Part: IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

Type: High and Low Side Driver

Key Specs:

• High side floating supply voltage (IR2110): 500V max.
• High side floating supply voltage (IR2113): 600V max.
• Gate drive supply range: 10V to 20V
• Output high short circuit pulsed current: 2.0 A (min)
• Output low short circuit pulsed current: 2.0 A (min)
• Turn-on propagation delay (typ.): 120 ns
• Turn-off propagation delay (typ.): 94 ns
• Delay matching (IR2110): 10 ns max.
• Delay matching (IR2113): 20 ns max.
• Allowable offset supply voltage transient (dV/dt): 50 V/ns

Features:

• Floating channel designed for bootstrap operation
• Fully operational to +500V or +600V
• Tolerant to negative transient voltage dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible
• Separate logic supply range from 3.3V to 20V
• Logic and power ground ±5V offset
• CMOS Schmitt-triggered inputs with pull-down
• Cycle by cycle edge-triggered shutdown logic
• Matched propagation delay for both channels
• Outputs in phase with inputs

Applications:

• null

Package:

• 14-Lead PDIP: dimensions null
• 16-Lead SOIC: dimensions null

• Floating channel designed for bootstrap operation Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset
• CMOS Schmitt-triggered inputs with pull-down
• Cycle by cycle edge-triggered shutdown logic
• Matched propagation delay for both channels
• Outputs in phase with inputs

VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25°C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 36 and 37.

Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 36 and 37.

Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.