GD32F103XX

Part: GigaDevice Semiconductor Inc. GD32F103xx

Type: Arm® Cortex®-M3 32-bit MCU

Description: A 32-bit general-purpose microcontroller based on the Arm® Cortex®-M3 RISC core operating at 108 MHz, featuring up to 3 MB Flash memory, 96 KB SRAM, and a wide range of peripherals.

Operating Conditions:

• Supply voltage: 2.6 to 3.6 V
• Operating temperature: -40 to +85 °C
• Max CPU frequency: 108 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max junction/storage temperature: +150 °C (Storage temperature)

Key Specs:

• Core: Arm® Cortex®-M3 32-bit RISC
• Max CPU Frequency: 108 MHz
• Flash Memory: Up to 3 MB
• SRAM Memory: Up to 96 KB
• ADC: Up to three 12-bit units
• DAC: Up to two 12-bit units
• Communication Interfaces: SPI, I2C, USART, UART, I2S, USBD, CAN, SDIO
• Timers: Up to ten 16-bit general-purpose, two 16-bit basic, two 16-bit advanced PWM timers

Features:

• Arm® Cortex®-M3 32-bit processor core
• Zero wait state Flash access
• Extensive range of enhanced I/Os
• Two APB buses
• Nested Vectored Interrupt Controller (NVIC)
• SysTick timer
• Advanced debug support
• Several power saving modes
• External Memory Controller (EXMC) for some variants

Applications:

• Industrial control
• Motor drives
• Power monitor and alarm systems
• Consumer and handheld equipment
• POS
• Vehicle GPS
• Video intercom
• PC peripherals

Package:

• LQFP144
• LQFP100
• LQFP64
• LQFP48
• QFN36

Figure 2-3. GD32F103Zx LQFP144 pinouts

Figure 2-4. GD32F103Vx LQFP100 pinouts

Figure 2-5. GD32F103Rx LQFP64 pinouts

Figure 2-6. GD32F103Cx LQFP48 pinouts

Figure 2-7. GD32F103Tx QFN36 pinouts

Table 4-34. ADC characteristics(For GD32F103x4/6/8/B devices)

GPIOx_MDy[1:0] bit value(3)	Parameter	Conditions	Typ	Unit
GPIOx_CTL->MDy[1:0]=10 (IO_Speed = 2MHz)	TRise/TFall	2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF	49.2	ns
		2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF	60
		2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF	70.4
GPIOx_CTL->MDy[1:0]=01 (IO_Speed = 10MHz)	TRise/TFall	2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF	23.4	ns
		2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF	27
		2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF	32
GPIOx_CTL->MDy[1:0]=11 (IO_Speed = 50MHz)	TRise/TFall	2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF	3.3	ns
		2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF	3.5
		2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF	3.6

⁽¹⁾ Based on characterization, not tested in production.

• (2) Guaranteed by design, not tested in production.
• (3) VREFP should always be equal to or less than VDDA, especially during power up.

Table 4-35. ADC characteristics(For GD32F103xC/D/E/F/G/I/K devices)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDDA(1)	Operating voltage	—	2.6	3.3	3.6	V
VIN(1)	ADC input voltage range	—	0	—	VREFP	V
VREFP(2) (3)	Positive Reference Voltage	—	2.6	—	VDDA	V
VREFN(2)	Negative Reference Voltage	—	—	VSSA	—	V
fADC(1)	ADC clock	—	0.6	—	14	MHz
fs(1)	Sampling rate	12-bit	0.04	—	1	MSP S
RAIN(2)	External input impedance	See Equation 1	—	—	219.8	kΩ
RADC(2)	Input sampling switch resistance	—	—	—	0.5	kΩ
CADC(2)	Input sampling capacitance	No pin/pad capacitance included	—	—	8	pF
tCAL(2)	Calibration time	fADC = 14 MHz	—	7.28	—	μs
ts(2)	Sampling time	fADC = 14 MHz	0.11	—	17.11	μs
tCONV(2)	Total conversion time (including sampling time)	12-bit	—	14	—	1/fADC
tSU(2)	Startup time	—	—	—	1	μs

• (1) Based on characterization, not tested in production.
• (2) Guaranteed by design, not tested in production.
• (3) VREFP should always be equal to or less than VDDA, especially during power up.

Equation 1: R_AIN max formula $R_AIN < frac{T_s}{f_ADCC_ADCln(2^N+2)} - R_ADCThe formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 4-36. ADC RAIN max for fADC = 14 MHz (For GD32F103x4/6/8/B devices)

• Ts (cycles) ts (μs) RAIN max (kΩ)
• 1.5 0.11 0.1
• 7.5 0.54 1.5
• 13.5 0.96 2.9
• 28.5 2.04 6.3
• 41.5 2.96 9.3
• 55.5 3.96 12.5
• 71.5 5.11 16.2
• 239.5 17.11 54.8

Table 4-37. ADC RAIN max for fADC = 14 MHz (For GD32F103xC/D/E/F/G/I/K devices)

• Ts (cycles) ts (μs) RAIN max (kΩ)
• 1.5 0.11 0.8
• 7.5 0.54 6.4
• 13.5 0.96 11.9
• 28.5 2.04 25.7
• 41.5 2.96 37.6
• 55.5 3.96 50.5
• 71.5 5.11 65.2
• 239.5 17.11 219.8

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly beyond the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Table 4-1. Absolute maximum ratings (1)(4)

Symbol	Parameter	Min	Max	Unit
VDD	External voltage range(2)	VSS - 0.3	VSS + 3.6	V
VDDA	External analog supply voltage	VSSA - 0.3	VSSA + 3.6	V
VBAT	External battery supply voltage	VSS - 0.3	VSS + 3.6	V
VIN	Input voltage on 5V tolerant pin(3)	VSS - 0.3	VDD + 3.6	V
	Input voltage on other I/O	VSS - 0.3	3.6	V
|ΔVDDX|	Variations between different VDD power pins	—	50	mV
|VSSX -VSS|	Variations between different ground pins	—	50	mV
IIO	Maximum current for GPIO pins	—	±25	mA
TA	Operating temperature range	-40	+85	°C
PD	Power dissipation at TA = 85°C of LQFP144	—	820	mW
	Power dissipation at TA = 85°C of LQFP100	—	697
	Power dissipation at TA = 85°C of LQFP64	—	647
	Power dissipation at TA = 85°C of LQFP48	—	621
	Power dissipation at TA = 85°C of QFN36	—	926
TSTG	Storage temperature range	-65	+150	°C
TJ	Maximum junction temperature	—	125	°C

⁽¹⁾ Guaranteed by design, not tested in production.

Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter "θ". For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface.

θJA: Thermal resistance, junction-to-ambient.

θJB: Thermal resistance, junction-to-board.

θJC: Thermal resistance, junction-to-case.

ᴪJB: Thermal characterization parameter, junction-to-board.

ᴪJT: Thermal characterization parameter, junction-to-top center.θ_JA = (T_J - T_A)/P_D tag{5-1}$

$θ_JB = (T_J - T_B)/P_D tag{5-2}$

$θ_JC = (T_J - T_C)/P_D tag{5-3}$

Where, T^J = Junction temperature.

T^A = Ambient temperature

T^B = Board temperature

T^C = Case temperature which is monitoring on package surface

P^D = Total power dissipation

θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature.

θJB is used to measure the heat flow resistance between the chip surface and the PCB board.

θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package).

Table 5-6. Package thermal characteristics(1)

Symbol	Condition	Package	Value	Unit
		LQFP144 LQFP100	48.76 57.42
θJA	Natural convection, 2S2P PCB	LQFP64 LQFP48 QFN36	61.80 64.40 43.20	°C/W
θJB	Cold plate, 2S2P PCB	LQFP144	35.00	°C/W
Symbol	Condition	Package LQFP100 LQFP64 LQFP48 QFN36 LQFP144 LQFP100	Value 31.68 42.83 42.32 16.51 12.03 13.85	Unit
θJC	Cold plate, 2S2P PCB	LQFP64 LQFP48 QFN36	21.98 22.47 16.18	°C/W
	Natural convection, 2S2P PCB	LQFP144 LQFP100	35.32 41.28
ᴪJB		LQFP64 LQFP48 QFN36 LQFP144	43.05 42.42 16.64 1.86	°C/W
ᴪJT		LQFP100	0.75
	Natural convection, 2S2P PCB	LQFP64 LQFP48 QFN36	1.58 1.74 1.07	°C/W

F A3 A1 A2 A DETAIL: F

SECTION B-B

Figure 5-1. LQFP144 package outline

Table 5-1. LQFP144 package dimensions

Symbol	Min	Typ	Max
A	_	_	1.60
A1	0.05		0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
b	0.18	_	0.26
b1	0.17	0.20	0.23
C	0.13	_	0.17
c1	0.12	0.13	0.14
D	21.80	22.00	22.20
D1	19.90	20.00	20.10
E	21.80	22.00	22.20
E1	19.90	20.00	20.10
e	_	0.50	_
L	0.45		0.75
L1	_	1.00	_
θ	0°	_	7°

5.2 LQFP100 package outline dimensions

Figure 5-3. LQFP100 package outline

Table 5-2. LQFP100 package dimensions

Symbol	Min	Typ	Max
A	—	—	1.60
A1	0.05	—	0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
b	0.18	—	0.26
b1	0.17	0.20	0.23
c	0.13	—	0.17
c1	0.12	0.13	0.14
D	15.80	16.00	16.20
D1	13.90	14.00	14.10
E	15.80	16.00	16.20
E1	13.90	14.00	14.10
e	—	0.50	—
eB	15.05	—	15.35
L	0.45	—	0.75
L1	—	1.00	—
θ	0°	—	7°

5.3 LQFP64 package outline dimensions

Figure 5-5. LQFP64 package outline

Table 5-3. LQFP64 package dimensions

Symbol	Min	Typ	Max
A	—	—	1.60
A1	0.05	—	0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
b	0.18	—	0.26
b1	0.17	0.20	0.23
c	0.13	—	0.17
c1	0.12	0.13	0.14
D	11.80	12.00	12.20
D1	9.90	10.00	10.10
E	11.80	12.00	12.20
E1	9.90	10.00	10.10
e	—	0.50	—
eB	11.25	—	11.45
L	0.45	—	0.75
L1	—	1.00	—
θ	0°	—	7°

Figure 5-6. LQFP64 recommended footprint

5.4 LQFP48 package outline dimensions

Figure 5-7. LQFP48 package outline

Table 5-4. LQFP48 package dimensions

Symbol	Min	Typ	Max
A	—	—	1.60
A1	0.05	—	0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
b	0.18	—	0.26
b1	0.17	0.20	0.23
c	0.13	—	0.17
c1	0.12	0.13	0.14
D	8.80	9.00	9.20
D1	6.90	7.00	7.10
E	8.80	9.00	9.20
E1	6.90	7.00	7.10
e	—	0.50	—
eB	8.10	—	8.25
L	0.45	—	0.75
L1	—	1.00	—
θ	0°	—	7°

Figure 5-8. LQFP48 recommended footprint

5.5 QFN36 package outline dimensions

Figure 5-9. QFN36 package outline

Table 5-5. QFN36 package dimensions

Symbol	Min	Typ	Max
A	0.80	0.85	0.90
A1	0	0.02	0.05
b	0.18	0.23	0.30
b1	—	0.16	—
c	0.18	0.20	0.23
D	5.90	6.00	6.10
D2	3.80	3.90	4.00
E	5.90	6.00	6.10
E2	3.80	3.90	4.00
e	—	0.50	—
h	0.30	0.35	0.40
L	0.50	0.55	0.60
L1	—	0.10	—
Nd	3.95	4.00	4.05
Ne	3.95	4.00	4.05

Figure 5-10. QFN36 recommended footprint

5.6 Thermal characteristics

Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter "θ". For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface.

θJA: Thermal resistance, junction-to-ambient.

θJB: Thermal resistance, junction-to-board.

θJC: Thermal resistance, junction-to-case.

ᴪJB: Thermal characterization parameter, junction-to-board.

ᴪJT: Thermal characterization parameter, junction-to-top center.θ_JA = (T_J - T_A)/P_D tag{5-1}$

$θ_JB = (T_J - T_B)/P_D tag{5-2}$

$θ_JC = (T_J - T_C)/P_D tag{5-3}$

Where, T^J = Junction temperature.

T^A = Ambient temperature

T^B = Board temperature

T^C = Case temperature which is monitoring on package surface

P^D = Total power dissipation

θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature.

θJB is used to measure the heat flow resistance between the chip surface and the PCB board.

θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package).

Table 5-6. Package thermal characteristics(1)

Symbol	Condition	Package	Value	Unit
		LQFP144 LQFP100	48.76 57.42
θJA	Natural convection, 2S2P PCB	LQFP64 LQFP48 QFN36	61.80 64.40 43.20	°C/W
θJB	Cold plate, 2S2P PCB	LQFP144	35.00	°C/W
Symbol	Condition	Package LQFP100 LQFP64 LQFP48 QFN36 LQFP144 LQFP100	Value 31.68 42.83 42.32 16.51 12.03 13.85	Unit
θJC	Cold plate, 2S2P PCB	LQFP64 LQFP48 QFN36	21.98 22.47 16.18	°C/W
	Natural convection, 2S2P PCB	LQFP144 LQFP100	35.32 41.28
ᴪJB		LQFP64 LQFP48 QFN36 LQFP144	43.05 42.42 16.64 1.86	°C/W
ᴪJT		LQFP100	0.75
	Natural convection, 2S2P PCB	LQFP64 LQFP48 QFN36	1.58 1.74 1.07	°C/W