EP4CGX15

Part: Altera Cyclone IV Devices

Type: Device

Key Specs:

• DisplayPort transmitter data rates: 1.62 Gbps and 2.7 Gbps
• Transceiver applications data rate: ≥ 2.97 Gbps
• Core Voltage for DDR2 SDRAM: 1.0-V
• Programmable PPM Detector options: ±500 PPM and ±1000 PPM
• PCIe interface: ×1

Features:

• Phase-locked loop (PLL) blocks
• Transceiver channels
• Row I/Os and high-speed serial interface (HSSI) I/Os
• Remote system upgrade (RSU) feature
• Hard IP block for PCIe interface
• Programmable PPM Detector in ALTGX MegaWizard Plug-In Manager
• External Memory Interface for DDR2 SDRAM

Applications:

• DisplayPort transmitter specifications
• SATA protocol
• Transceiver applications
• PCIe ×1 interface
• DDR2 SDRAM external memory

Package:

• F484 package: null

You may not meet the protocol jitter specification or may have a higher bit error rate (BER) if you do not use the following guidelines.

If your transceiver applications run at ≥ 2.97 Gbps data rate, you must ground specific pins (refer to Table 3) next to the reference clock directly through the via under the device to the PCB ground plane on your board. You also must assign the specific pins to ground in the Quartus II software. To minimize the impact listed in Table 3, Altera recommends using REFCLK[1..0] and REFCLK[5..4] reference clocks before using REFCLK2 and REFCLK3 reference clocks.

There is no action required and no performance degradation for input reference clocks that are used to drive transceiver channels at < 2.97 Gbps data rates.

Table 3 lists the reference clock pins and the associated I/O pins to be grounded for transceiver applications that run at ≥ 2.97 Gbps data rate.

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver Applications (Part 1 of 3)

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver Applications (Part 2 of 3)

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver Applications (Part 3 of 3)

Notes to Table 3:

• (1) The unused adjacent reference clock pins in the same bank can only be used as differential input clock.
• (2) The unused adjacent reference clock pins in Bank 4 (Package F23: AA12 and AB12 pins, package F27: AF13 and AF14 pins, and package F31: AJ16 and AK16 pins) can only be used as differential input clock.
• (3) The unused adjacent reference clock pins in Bank 7 (Package F27: A14 and B14 pins and package F31: A15 and B15 pins) can only be used as differential input clock.
• (4) You can only use REFCLK2 in Bank 3A for transceiver block GXBL0 and REFCLK3 in Bank 8A for transceiver block GXBL1.
• (5) Do not tie this pin to ground if it is used for configuration or a dedicated function in User mode. Dedicated functions include using the DATA1/ASDO, ncso, and DATA0 pins for EPCS access and the crc_error pin for a cyclic redundancy check (CRC) error function. Do not use this pin as a user I/O in User mode.
• (6) Do not toggle the CLKUSR pin in User mode. Reassign the CLKUSR pin to another I/O pin if it is being used in User mode.
• (7) You can alternatively use zero delay buffer (ZDB) mode with other phase-locked loops (PLLs).
• (8) You can alternatively use other DQ/DQS groups or wraparound DQ/DQS groups. For more information about wraparound DQ/DQS performance, refer to the External Memory Interface Spec Estimator page on Altera website.

Table 4 lists the Quartus II software support planning.

Table 4. Quartus II Software Planned Support

f The Cyclone IV Device Family Pin Connection Guidelines has been updated with the guidelines for transceiver applications that run at 2.97 Gbps data rate.