EP4CGX30

Part: Cyclone IV Devices — Altera Corporation

Type: Field-Programmable Gate Array (FPGA)

Description: An errata sheet detailing known issues and their resolutions or workarounds for Altera Cyclone IV and Cyclone IV GX FPGA devices, covering PLL, ESD, transceiver, memory interface, and configuration features.

Operating Conditions:

• Operating temperature: not applicable (errata sheet)

Absolute Maximum Ratings:

• Max junction/storage temperature: not applicable (errata sheet)

Key Specs:

• HBM ESD Class: 0 (for EP4CGX15 and EP4CGX30, except F484 package)
• DisplayPort Transmitter Data Rates: 1.62 Gbps, 2.7 Gbps
• Transceiver Data Rate for Pin Guidelines: ≥ 2.97 Gbps
• SATA CDR PPM Tolerance (AsyncSSC not enabled): ±350 PPM (EP4CGX15, EP4CGX22, EP4CGX30 F169/F324, EP4CGX110, EP4CGX150), ±200 PPM (EP4CGX30 F484, EP4CGX50, EP4CGX75)
• Programmable PPM Detector Supported Range: ±62.5 PPM to ±300 PPM

Features:

• Phase-Locked Loop (PLL) blocks
• Human Body Model (HBM) Electrostatic Discharge (ESD) protection
• DisplayPort transceiver
• Asynchronous Spread Spectrum Clock (SSC) modulation tracking
• Remote System Upgrade (RSU)
• PCIe ×1 interface with Hard IP block
• External Memory Interface for DDR2 SDRAM

Applications:

• Transceiver applications (DisplayPort, SATA, V-by-one HS, PCIe Gen1)
• Remote system upgrade
• External memory interfaces

Package:

• F484
• F169
• F324
• F23
• F27
• F31

You may not meet the protocol jitter specification or may have a higher bit error rate (BER) if you do not use the following guidelines.

If your transceiver applications run at 2.97 Gbps data rate, you must ground specific pins (refer to Table 3) next to the reference clock directly through the via under the device to the PCB ground plane on your board. You also must assign the specific pins to ground in the Quartus II software. To minimize the impact listed in Table 3, Altera recommends using REFCLK[1..0] and REFCLK[5..4] reference clocks before using REFCLK2 and REFCLK3 reference clocks.

There is no action required and no performance degradation for input reference clocks that are used to drive transceiver channels at 2.97 Gbps data rates.

Table 3 lists the reference clock pins and the associated I/O pins to be grounded for transceiver applications that run at 2.97 Gbps data rate.

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for 2.97 Gbps Transceiver Applications (Part 1 of 3)

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for 2.97 Gbps Transceiver Applications (Part 2 of 3)

Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for 2.97 Gbps Transceiver Applications (Part 3 of 3)

Notes to Table 3:

• (1) The unused adjacent reference clock pins in the same bank can only be used as differential input clock.
• (2) The unused adjacent reference clock pins in Bank 4 (Package F23: AA12 and AB12 pins, package F27: AF13 and AF14 pins, and package F31: AJ16 and AK16 pins) can only be used as differential input clock.
• (3) The unused adjacent reference clock pins in Bank 7 (Package F27: A14 and B14 pins and package F31: A15 and B15 pins) can only be used as differential input clock.
• (4) You can only use REFCLK2 in Bank 3A for transceiver block GXBL0 and REFCLK3 in Bank 8A for transceiver block GXBL1.
• (5) Do not tie this pin to ground if it is used for configuration or a dedicated function in User mode. Dedicated functions include using the DATA1 / ASDO , nCSO , and DATA0 pins for EPCS access and the crc_error pin for a cyclic redundancy check (CRC) error function. Do not use this pin as a user I/O in User mode.
• (6) Do not toggle the CLKUSR pin in User mode. Reassign the CLKUSR pin to another I/O pin if it is being used in User mode.
• (7) You can alternatively use zero delay buffer (ZDB) mode with other phase-locked loops (PLLs).
• (8) You can alternatively use other DQ/DQS groups or wraparound DQ/DQS groups. For more information about wraparound DQ/DQS performance, refer to the External Memory Interface Spec Estimator page on Altera website.

Table 4 lists the Quartus II software support planning.

Table 4. Quartus II Software Planned Support

The Cyclone IV Device Family Pin Connection Guidelines has been updated with the guidelines for transceiver applications that run at 2.97 Gbps data rate.