DRV8825
DRV8825 Stepper Motor Controller IC
Manufacturer
ti
Overview
Part: DRV8825
Type: Stepper Motor Controller IC
Key Specs:
- Operating Supply Voltage Range: 8.2-V to 45-V
- Maximum Drive Current: 2.5-A at 24 V and $T_A = 25^{\circ}C$
- Microstepping: Up to 1/32 Microstepping
Features:
- PWM Microstepping Stepper Motor Driver
- Built-In Microstepping Indexer
- Multiple Decay Modes (Mixed, Slow, Fast)
- Simple STEP/DIR Interface
- Low Current Sleep Mode
- Built-In 3.3-V Reference Output
- Small Package and Footprint
- Overcurrent Protection (OCP)
- Thermal Shutdown (TSD)
- VM Undervoltage Lockout (UVLO)
- Fault Condition Indication Pin (nFAULT)
Applications:
- Automatic Teller Machines
- Money Handling Machines
- Video Security Cameras
- Printers
- Scanners
- Office Automation Machines
- Gaming Machines
- Factory Automation
- Robotics
Package:
- HTSSOP (28): 9.70 mm × 6.40 mm
Features
- PWM Microstepping Stepper Motor Driver
- Built-In Microstepping Indexer
- Up to 1/32 Microstepping
- Multiple Decay Modes
- Mixed Decay
- Slow Decay
- Fast Decay
- 8.2-V to 45-V Operating Supply Voltage Range
- 2.5-A Maximum Drive Current at 24 V and $T_A = 25^{\circ}C$
- Simple STEP/DIR Interface
- Low Current Sleep Mode
- Built-In 3.3-V Reference Output
- Small Package and Footprint
- Protection Features
- Overcurrent Protection (OCP)
- Thermal Shutdown (TSD)
- VM Undervoltage Lockout (UVLO)
- Fault Condition Indication Pin (nFAULT)
Applications
- Automatic Teller Machines
- Money Handling Machines
- Video Security Cameras
- Printers
- Scanners
- Office Automation Machines
- Gaming Machines
- Factory Automation
- Robotics
3 Description
The DRV8825 provides an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device has two H-bridge drivers and a microstepping indexer, and is intended to drive a bipolar stepper motor. The output driver block consists of N-channel power MOSFET's configured as full H-bridges to drive the motor windings. The DRV8825 is capable of driving up to 2.5 A of current from each output (with proper heat sinking, at 24 V and 25°C).
A simple STEP/DIR interface allows easy interfacing to controller circuits. Mode pins allow for configuration of the motor in full-step up to 1/32-step modes. Decay mode is configurable so that slow decay, fast decay, or mixed decay can be used. A low-power sleep mode is provided which shuts down internal circuitry to achieve very low quiescent current draw. This sleep mode can be set using a dedicated nSLEEP
shutdown functions are provided overcurrent, short circuit, under voltage lockout and over temperature. Fault conditions are indicated via the nFAULT pin.
Pin Configuration
Pin Functions
| PIN | EXTERNAL COMPONENTS | |||
|---|---|---|---|---|
| NAME | NO. | I/O(1) | DESCRIPTION | OR CONNECTIONS |
| POWER AND GROUND | ||||
| CP1 | 1 | I/O | Charge pump flying capacitor | |
| CP2 | 2 | I/O | Charge pump flying capacitor | Connect a 0.01-μF 50-V capacitor between CP1 and CP2. |
| GND | 14, 28 | — | Device ground | |
| VCP | 3 | I/O | High-side gate drive voltage | Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. |
| VMA | 4 | — | Bridge A power supply | Connect to motor supply (8.2 to 45 V). Both pins must be |
| VMB | 11 | — | Bridge B power supply | connected to the same supply, bypassed with a 0.1-µF capacitor to GND, and connected to appropriate bulk capacitance. |
| V3P3OUT | 15 | O | 3.3-V regulator output | Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. |
| CONTROL | ||||
| AVREF | 12 | I | Bridge A current set reference input | Reference voltage for winding current set. Normally AVREF and |
| BVREF | 13 | I | Bridge B current set reference input | BVREF are connected to the same voltage. Can be connected to V3P3OUT. |
| DECAY | 19 | I | Decay mode | Low = slow decay, open = mixed decay, high = fast decay. Internal pulldown and pullup. |
| DIR | 20 | I | Direction input | Level sets the direction of stepping. Internal pulldown. |
| MODE0 | 24 | I | Microstep mode 0 | |
| MODE1 | 25 | I | Microstep mode 1 | MODE0 through MODE2 set the step mode - full, 1/2, 1/4, 1/8/ 1/16, or 1/32 step. Internal pulldown. |
| MODE2 | 26 | I | Microstep mode 2 | |
| NC | 23 | — | No connect | Leave this pin unconnected. |
| nENBL | 21 | I | Enable input | Logic high to disable device outputs and indexer operation, logic low to enable. Internal pulldown. |
| nRESET | 16 | I | Reset input | Active-low reset input initializes the indexer logic and disables the H-bridge outputs. Internal pulldown. |
| nSLEEP | 17 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. |
| STEP | 22 | I | Step input | Rising edge causes the indexer to move one step. Internal pulldown. |
| STATUS | ||||
| nFAULT | 18 | OD | Fault | Logic low when in fault condition (overtemp, overcurrent) |
| (1) Directions: I = input, O = output, OD = open-drain output, IO = input/output |
Pin Functions (continued)
| PII | N | I/O (1) | DESCRIPTION | EXTERNAL COMPONENTS | |--------|-----|--------------------|--------------------------|-------------------------------------------------|--| | NAME | NO. | 1/0 ( / | DESCRIPTION | OR CONNECTIONS | | nHOME | 27 | OD | Home position | Logic low when at home state of step table | | OUTPUT | | AOUT1 | 5 | 0 | Bridge A output 1 | Connect to bipolar stepper motor winding A. | | AOUT2 | 7 | 0 | Bridge A output 2 | Positive current is AOUT1 → AOUT2 | | BOUT1 | 10 | 0 | Bridge B output 1 | Connect to bipolar stepper motor winding B. | | BOUT2 | 8 | 0 | Bridge B output 2 | Positive current is BOUT1 → BOUT2 | | ISENA | 6 | I/O | Bridge A ground / Isense | Connect to current sense resistor for bridge A. | | ISENB | 9 | I/O | Bridge B ground / Isense | Connect to current sense resistor for bridge B. |
Electrical Characteristics
over operating free-air temperature range of -40°C to 85°C (unless otherwise noted)
| PARAMETER | ge of –40°C to 85°C (unless otherwise noted) TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | SUPPLIES | |||||
| I VM | VM operating supply current | V (VMx) = 24 V | 5 | 8 | mA | |
| I VMQ | VM sleep mode supply current | $V_{(VMX)} = 24 \text{ V}$ | 10 | 20 | μA | |
| JT REGULATOR | (VIVIX) — Z I V | 20 | μπ | |||
| V 3P3 | V3P3OUT voltage | IOUT = 0 to 1 mA | 3.2 | 3.3 | 3.4 | V |
| LEVEL INPUTS | 1001 - 0 10 1 11114 | 5.2 | 0.0 | 5.4 | V | |
| V IL | Input low voltage | 0 | 0.7 | V | ||
| V IH | Input high voltage | 2.2 | 5.25 | V | ||
| Input hysteresis | 0.3 | 0.45 | 0.6 | V | ||
| V HYS | · · · · | VIN = 0 | -20 | 0.43 | 20 | μA |
| I IL | Input low current | -20 | • | |||
| I IH | Input high current | VIN = 3.3 V | 400 | 100 | μA | |
| R PD | Internal pulldown resistance | N OUTDUTO) | 100 | kΩ | ||
| , nFAULT OUTPUTS (OPEN-DRAI | , | 0.5 | ., | |||
| V OL | Output low voltage | I O = 5 mA | 0.5 | V | ||
| I OH | Output high leakage current | V O = 3.3 V | 1 | μA | ||
| DECAY | T | |||||
| V IL | Input low threshold voltage | For slow decay mode | 0.8 | V | ||
| V IH | Input high threshold voltage | For fast decay mode | 2 | V | ||
| I IN | Input current | -40 | 40 | μΑ | ||
| R PU | Internal pullup resistance (to 3.3 V) | 130 | kΩ | |||
| R PD | Internal pulldown resistance | 80 | kΩ | |||
| H-BRID | GE FETS | |||||
| LIC FFT on registeres | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 25^{\circ}\text{C}$ | 0.2 | ||||
| Ь | HS FET on resistance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 85^{\circ}\text{C}$ | 0.25 | 0.32 | 0 | |
| R DS(ON) | LC FFT on registance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 25^{\circ}\text{C}$ | 0.2 | Ω | ||
| LS FET on resistance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 85^{\circ}\text{C}$ | 0.25 | 0.32 | |||
| I OFF | Off-state leakage current | -20 | 20 | μA | ||
| MOTOR | DRIVER | |||||
| $f_{PWM}$ | Internal current control PWM frequency | 30 | kHz | |||
| t BLANK | Current sense blanking time | 4 | μs | |||
| t R | Rise time | 30 | 200 | ns | ||
| t F | Fall time | 30 | 200 | ns | ||
| - | CTION CIRCUITS | 1 | 1 | |||
| V UVLO | VM undervoltage lockout voltage | V (VMx) rising | 7.8 | 8.2 | V | |
| I OCP | Overcurrent protection trip level | () | 3 | Α | ||
| t DEG | Overcurrent deglitch time | 3 | μs | |||
| t TSD | Thermal shutdown temperature | Die temperature | 150 | 160 | 180 | °C |
| NT CONTROL | r | |||||
| I REF | xVREF input current | $V_{(XVREF)} = 3.3 \text{ V}$ | -3 | 3 | μA | |
| V TRIP | xISENSE trip voltage | $V_{(XVREF)} = 3.3 \text{ V}, 100% \text{ current setting}$ | 635 | 660 | 685 | mV |
| TRIP | p | $V_{(XVREF)} = 3.3 \text{ V}, 5% \text{ current setting}$ | -25% | 25% | ||
| Current trip popular | $V_{(XVREF)} = 3.3 \text{ V}, 3% \text{ current setting}$ $V_{(XVREF)} = 3.3 \text{ V}, 10% \text{ to } 34% \text{ current setting}$ | -15% | 15% | |||
| $\Delta I_{TRIP}$ | Current trip accuracy (relative to programmed value) | $V_{(XVREF)} = 3.3 \text{ V}$ , 10% to 34% current setting $V_{(XVREF)} = 3.3 \text{ V}$ , 38% to 67% current setting | -10% | 10% | ||
| i | ( | V(XVREF) - 3.3 V, 3070 to 07 70 current Setting | 10 /0 | |||
| $V_{(XVREF)} = 3.3 \text{ V}$ , 71% to 100% current setting | -5% | 5% | ||||
Absolute Maximum Ratings
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| ., | Power supply voltage | -0.3 | 47 | V |
| $V_{(VMx)}$ | Power supply ramp rate | 1 | V/µs | |
| Digital pin voltage | -0.5 | 7 | V | |
| V (xVREF) | Input voltage | -0.3 | 4 | V |
| ISENSEx pin voltage (3) | -0.8 | 0.8 | V | |
| Peak motor drive output current, t < 1 μs | Inte | ernally limited | Α | |
| Continuous motor drive output current (4) | 0 | 2.5 | Α | |
| Continuous total power dissipation | See Therm | al Information | ||
| TJ | Operating junction temperature range | -40 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
- (2) All voltage values are with respect to network ground terminal.
- (3) Transients of ±1 V for less than 25 ns are acceptable
- (4) Power dissipation and thermal limits must be observed.
7.2 Handling Ratings
| | | | MIN | MAX | UNIT | |--------------------|---------------|-------------------------------------------------------------------------------|-------|------|------|--| | T stg | Storage tempe | erature range | -60 | 150 | °C | | V | Electrostatic | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | -2000 | 2000 | / | | V (ESD) | discharge | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) | -500 | 500 | V |
- (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
- (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | NOM MAX | UNIT | ||
|---|---|---|---|---|
| $V_{(VMx)}$ | Motor power supply voltage range (1) | 8.2 | 45 | V |
| V (VREF) | VREF input voltage (2) | 1 | 3.5 | V |
| I V3P3 | V3P3OUT load current | 0 | 1 | mA |
(1) All $V_M$ pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 to 1 V, but accuracy is degraded.
7.4 Thermal Information
| | | DRV8825 | |-----------------------|-------------------------------------------------------------|---------|------| | | THERMAL METRIC (1) | PWP | UNIT | | | | 28 PINS | | $R_{\theta JA}$ | Junction-to-ambient thermal resistance (2) | 31.6 | | R 0JC(top) | Junction-to-case (top) thermal resistance (3) | 15.9 | | $R_{\theta JB}$ | Junction-to-board thermal resistance (4) | 5.6 | 9000 | | ΨЈT | Junction-to-top characterization parameter (5) | 0.2 | °C/W | | ΨЈB | Junction-to-board characterization parameter (6) | 5.5 | | $R_{\theta JC(bot)}$ | Junction-to-case (bottom) thermal resistance (7) | 1.4 |
- (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
- (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
- (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
- (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
- (5) The junction-to-top characterization parameter, $\psi_{JT}$ , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining $\theta_{JA}$ , using a procedure described in JESD51-2a (sections 6 and 7).
- (6) The junction-to-board characterization parameter, $\psi_{JB}$ , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining $\theta_{JA}$ , using a procedure described in JESD51-2a (sections 6 and 7).
- (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
7.5 Electrical Characteristics
over operating free-air temperature range of -40°C to 85°C (unless otherwise noted)
| PARAMETER | ge of –40°C to 85°C (unless otherwise noted) TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | SUPPLIES | |||||
| I VM | VM operating supply current | V (VMx) = 24 V | 5 | 8 | mA | |
| I VMQ | VM sleep mode supply current | $V_{(VMX)} = 24 \text{ V}$ | 10 | 20 | μA | |
| JT REGULATOR | (VIVIX) — Z I V | 20 | μπ | |||
| V 3P3 | V3P3OUT voltage | IOUT = 0 to 1 mA | 3.2 | 3.3 | 3.4 | V |
| LEVEL INPUTS | 1001 - 0 10 1 11114 | 5.2 | 0.0 | 5.4 | V | |
| V IL | Input low voltage | 0 | 0.7 | V | ||
| V IH | Input high voltage | 2.2 | 5.25 | V | ||
| Input hysteresis | 0.3 | 0.45 | 0.6 | V | ||
| V HYS | · · · · | VIN = 0 | -20 | 0.43 | 20 | μA |
| I IL | Input low current | -20 | • | |||
| I IH | Input high current | VIN = 3.3 V | 400 | 100 | μA | |
| R PD | Internal pulldown resistance | N OUTDUTO) | 100 | kΩ | ||
| , nFAULT OUTPUTS (OPEN-DRAI | , | 0.5 | ., | |||
| V OL | Output low voltage | I O = 5 mA | 0.5 | V | ||
| I OH | Output high leakage current | V O = 3.3 V | 1 | μA | ||
| DECAY | T | |||||
| V IL | Input low threshold voltage | For slow decay mode | 0.8 | V | ||
| V IH | Input high threshold voltage | For fast decay mode | 2 | V | ||
| I IN | Input current | -40 | 40 | μΑ | ||
| R PU | Internal pullup resistance (to 3.3 V) | 130 | kΩ | |||
| R PD | Internal pulldown resistance | 80 | kΩ | |||
| H-BRID | GE FETS | |||||
| LIC FFT on registeres | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 25^{\circ}\text{C}$ | 0.2 | ||||
| Ь | HS FET on resistance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 85^{\circ}\text{C}$ | 0.25 | 0.32 | 0 | |
| R DS(ON) | LC FFT on registance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 25^{\circ}\text{C}$ | 0.2 | Ω | ||
| LS FET on resistance | $V_{(VMx)} = 24 \text{ V}, I_O = 1 \text{ A}, T_J = 85^{\circ}\text{C}$ | 0.25 | 0.32 | |||
| I OFF | Off-state leakage current | -20 | 20 | μA | ||
| MOTOR | DRIVER | |||||
| $f_{PWM}$ | Internal current control PWM frequency | 30 | kHz | |||
| t BLANK | Current sense blanking time | 4 | μs | |||
| t R | Rise time | 30 | 200 | ns | ||
| t F | Fall time | 30 | 200 | ns | ||
| - | CTION CIRCUITS | 1 | 1 | |||
| V UVLO | VM undervoltage lockout voltage | V (VMx) rising | 7.8 | 8.2 | V | |
| I OCP | Overcurrent protection trip level | () | 3 | Α | ||
| t DEG | Overcurrent deglitch time | 3 | μs | |||
| t TSD | Thermal shutdown temperature | Die temperature | 150 | 160 | 180 | °C |
| NT CONTROL | r | |||||
| I REF | xVREF input current | $V_{(XVREF)} = 3.3 \text{ V}$ | -3 | 3 | μA | |
| V TRIP | xISENSE trip voltage | $V_{(XVREF)} = 3.3 \text{ V}, 100% \text{ current setting}$ | 635 | 660 | 685 | mV |
| TRIP | p | $V_{(XVREF)} = 3.3 \text{ V}, 5% \text{ current setting}$ | -25% | 25% | ||
| Current trip popular | $V_{(XVREF)} = 3.3 \text{ V}, 3% \text{ current setting}$ $V_{(XVREF)} = 3.3 \text{ V}, 10% \text{ to } 34% \text{ current setting}$ | -15% | 15% | |||
| $\Delta I_{TRIP}$ | Current trip accuracy (relative to programmed value) | $V_{(XVREF)} = 3.3 \text{ V}$ , 10% to 34% current setting $V_{(XVREF)} = 3.3 \text{ V}$ , 38% to 67% current setting | -10% | 10% | ||
| i | ( | V(XVREF) - 3.3 V, 3070 to 07 70 current Setting | 10 /0 | |||
| $V_{(XVREF)} = 3.3 \text{ V}$ , 71% to 100% current setting | -5% | 5% | ||||
Recommended Operating Conditions
| MIN | NOM MAX | UNIT | ||
|---|---|---|---|---|
| $V_{(VMx)}$ | Motor power supply voltage range (1) | 8.2 | 45 | V |
| V (VREF) | VREF input voltage (2) | 1 | 3.5 | V |
| I V3P3 | V3P3OUT load current | 0 | 1 | mA |
(1) All $V_M$ pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 to 1 V, but accuracy is degraded.
Thermal Information
| | | DRV8825 | |-----------------------|-------------------------------------------------------------|---------|------| | | THERMAL METRIC (1) | PWP | UNIT | | | | 28 PINS | | $R_{\theta JA}$ | Junction-to-ambient thermal resistance (2) | 31.6 | | R 0JC(top) | Junction-to-case (top) thermal resistance (3) | 15.9 | | $R_{\theta JB}$ | Junction-to-board thermal resistance (4) | 5.6 | 9000 | | ΨЈT | Junction-to-top characterization parameter (5) | 0.2 | °C/W | | ΨЈB | Junction-to-board characterization parameter (6) | 5.5 | | $R_{\theta JC(bot)}$ | Junction-to-case (bottom) thermal resistance (7) | 1.4 |
- (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
- (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
- (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
- (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
- (5) The junction-to-top characterization parameter, $\psi_{JT}$ , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining $\theta_{JA}$ , using a procedure described in JESD51-2a (sections 6 and 7).
- (6) The junction-to-board characterization parameter, $\psi_{JB}$ , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining $\theta_{JA}$ , using a procedure described in JESD51-2a (sections 6 and 7).
- (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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