DRV8353RSRGZR

Three-Phase Smart Gate Driver

The DRV8353RSRGZR is a three-phase smart gate driver from Texas Instruments. View the full DRV8353RSRGZR datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Key Specifications

Parameter	Value
Applications	Brushless DC (BLDC)
Output Current	25mA
Function	Controller - Commutation, Direction Management
Interface	SPI
Motor Type (DC)	Brushless DC (BLDC)
Motor Type (Stepper)	Multiphase
Mounting Type	Surface Mount
Operating Temperature	-40°C ~ 125°C (TA)
Output Configuration	Pre-Driver - Half Bridge (3)
Package / Case	48-VFQFN Exposed Pad
Packaging	MouseReel
Packaging	MouseReel
Standard Pack Qty	2500
Standard Pack Qty	2500
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Supplier Device Package	48-VQFN (7x7)
Diode Technology	Power MOSFET
Load Voltage	9V ~ 75V
Supply Voltage	6V ~ 95V

Overview

Part: DRV835x — Texas Instruments

Type: 100-V Three-Phase Smart Gate Driver

Description: The DRV835x family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications, featuring smart gate drive architecture, optional integrated current shunt amplifiers, and an optional buck regulator, supporting 9 to 100-V operation.

Operating Conditions:

Supply voltage: 9–100 V
Operating temperature: -40 to +125 °C
Buck regulator operating voltage: 6 to 95 V
Buck regulator output capability: 2.5 to 75 V, 350 mA

Absolute Maximum Ratings:

Max supply voltage (VM): 80 V
Max buck regulator supply voltage (VIN): 100 V
Max junction temperature: 150 °C
Max storage temperature: 150 °C

Key Specs:

Peak source current: 50 mA to 1 A
Peak sink current: 100 mA to 2 A
Buck regulator output current: 350 mA
Shunt amplifier adjustable gain: 5, 10, 20, 40 V/V
Low-power sleep mode current: 20 μA (at VVM = 48-V)
MOSFET drain sense pin voltage (VDRAIN): -0.3 to 102 V
MOSFET drain sense pin voltage slew rate (VDRAIN): 0 to 2 V/μs

Features:

9 to 100-V, Triple half-bridge gate driver
Optional integrated buck regulator
Optional triple low-side current shunt amplifiers
Smart gate drive architecture with adjustable slew rate control
VGS handshake and minimum dead-time insertion
Integrated gate driver power supplies (high-side doubler charge pump, low-side linear regulator)
6x, 3x, 1x, and independent PWM modes
SPI or hardware interface available
Integrated protection features (UVLO, GDUV, OCP, shoot-through prevention, GDF, OTW/OTSD, nFAULT)

Applications:

3-phase brushless-DC (BLDC) motor modules
Fans, blowers, and pumps
E-Bikes, E-scooters, and E-mobility
Power and garden tools, lawn mowers
Drones, robotics, and RC toys
Factory automation and textile machines

Package:

WQFN (32) 5.00 mm × 5.00 mm
VQFN (48) 7.00 mm × 7.00 mm
WQFN (40) 6.00 mm × 6.00 mm

Features

1 · 9 to 100-V, Triple half-bridge gate driver
-Optional integrated buck regulator
-Optional triple low-side current shunt amplifiers
Smart gate drive architecture
-Adjustable slew rate control for EMI performance
-VGS handshake and minimum dead-time insertion to prevent shoot-through
-50-mA to 1-A peak source current
-100-mA to 2-A peak sink current
-dV/dt mitigation through strong pulldown
Integrated gate driver power supplies
-High-side doubler charge pump For 100% PWM duty cycle control
-Low-side linear regulator
Integrated LM5008A buck regulator
-6 to 95-V operating voltage range
-2.5 to 75-V, 350-mA output capability
Integrated triple current shunt amplifiers
-Adjustable gain (5, 10, 20, 40 V/V)
-Bidirectional or unidirectional support
6x, 3x, 1x, and independent PWM modes
-Supports 120° sensored operation
SPI or hardware interface available
Low-power sleep mode (20 μA at VVM = 48-V)
Integrated protection features
-VM undervoltage lockout (UVLO)
-Gate drive supply undervoltage (GDUV)
-MOSFET VDS overcurrent protection (OCP)
-MOSFET shoot-through prevention
-Gate driver fault (GDF)
-Thermal warning and shutdown (OTW/OTSD)
-Fault condition indicator (nFAULT)

Applications

3-phase brushless-DC (BLDC) motor modules
Fans, blowers, and pumps
E-Bikes, E-scooters, and E-mobility
Power and garden tools, lawn mowers
Drones, robotics, and RC toys
Factory automation and textile machines

DRV8350, DRV8350R DRV8353, DRV8353R

SLVSDY6A -AUGUST 2018-REVISED JUNE 2019

Pin Configuration

DRV8353RSRGZR Pinout

Package: 48-VFQFN Exposed Pad

Pin Number	Pin Name	Type	Description
1	GND	PWR	Ground
2	VGLS	PWR	Gate Driver Low-Side Supply
3	CPL	PWR	Charge Pump Low
4	CPH	PWR	Charge Pump High
6	VDRAIN	I	Drain Voltage Sense
7	VCP	PWR	Charge Pump Supply
8	GHA	O	Gate Driver High A
9	SHA	I	Shunt Sense High A
10	GLA	O	Gate Driver Low A
11	SLA	I	Shunt Sense Low A
12	NC	NC	No Connection
13	NC	NC	No Connection
14	SLB	I	Shunt Sense Low B
15	GLB	O	Gate Driver Low B
16	SHB	I	Shunt Sense High B
17	GHB	O	Gate Driver High B
18	GHC	O	Gate Driver High C
19	SHC	I	Shunt Sense High C
20	GLC	O	Gate Driver Low C
21	SLC	I	Shunt Sense Low C
22	NC	NC	No Connection
23	NC	NC	No Connection
24	NC	NC	No Connection
25	NC	NC	No Connection
26	NC	NC	No Connection
27	AGND	PWR	Analog Ground
28	nFAULT	OD	Fault Output (Open-Drain)
29	SDO	OD	Serial Data Output (Open-Drain)
30	SDI	I	Serial Data Input
31	SCLK	I	Serial Clock
32	nSCS	I	Serial Chip Select (Active Low)
33	ENABLE	I	Enable Input
34	INHA	I	Input High A
35	INLA	I	Input Low A
36	INHB	I	Input High B
37	INLB	I	Input Low B
38	INHC	I	Input High C
39	INLC	I	Input Low C
40	DVDD	PWR	Digital Supply Voltage
41	DGND	PWR	Digital Ground
42	SW	O	Switch Output
44	VCC	PWR	Logic Supply Voltage
45	BST	PWR	Bootstrap Supply
46	RCL	I	RC Low-Side Filter
47	RT/SD	I	RC Time Constant / Shutdown
48	FB	I	Feedback Input

Notes

Pin 5, 43: Not listed in source table; likely exposed pad or reserved.
DRV8353RSRGZR variant: This pinout is extracted from the DRV8350RS column of the source table, which matches the DRV8353RSRGZR part number (SPI-enabled variant). Pins 29–32 (SDO, SDI, SCLK, nSCS) are SPI interface pins specific to this variant.
Pins 30, 32, 29, 31 in DRV8350RH variant: The DRV8350RH variant uses different pins for MODE (29), IDRIVE (30), and VDS (31); these are not present in the DRV8353RSRGZR variant.
Open-Drain outputs: nFAULT and SDO are open-drain outputs and require external pull-up resistors.

Electrical Characteristics

at TA = -40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)	POWER SUPPLIES (DVDD, VCP, VGLS, VM)
I VM	VM operating supply current	V VM = V VDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V		8.5	13	mA
I VDRAIN	VDRAIN operating supply current	V VM = V VDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V ENABLE = 0 V, V VM = V VDRAIN = 48 V, T A = 25°C		1.9 20	4 40	mA
I SLEEP	Sleep mode supply current	ENABLE = 0 V, V VM = V VDRAIN = 48 V, T A = 125°C			100	μA
t RST	Reset pulse time	ENABLE = 0 V period to reset faults	5		40	μs
t WAKE	Turnon time	V VM > V UVLO , ENABLE = 3.3 V to outputs ready			1	ms
t SLEEP	Turnoff time	ENABLE = 0 V to device sleep mode			1	ms
V DVDD	DVDD regulator voltage	I DVDD = 0 to 10 mA	4.75	5	5.25	V
V VCP	VCP operating voltage with respect to VDRAIN	V VM = 15 V, I VCP = 0 to 25 mA	9	10.5	12	V
		V VM = 12 V, I VCP = 0 to 20 mA	7.5	10	11.5
		V VM = 10 V, I VCP = 0 to 15 mA	6	8	9.5
		V VM = 9 V, I VCP = 0 to 10 mA	5.5	7.5	8.5
V VGLS	VGLS operating voltage	V VM = 15 V, I VGLS = 0 to 25 mA	13	14.5	16
		V VM = 12 V, I VGLS = 0 to 20 mA	10	11.5	12.5	V
	with respect to GND	V VM = 10 V, I VGLS = 0 to 15 mA	8	9.5	10.5
		V VM = 9 V, I VGLS = 0 to 10 mA	7	8.5	9.5
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS,	LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS,	SCLK, SDI)
V IL	Input logic low voltage		0		0.8	V
V IH	Input logic high voltage		1.5		5.5	V
V HYS	Input logic hysteresis			100		mV
I IL	Input logic low current	V VIN = 0 V	-5		5	μA
I IH	Input logic high current	V VIN = 5 V		50	70	μA
R PD	Pulldown resistance	To GND		100		k Ω
t PD	Propagation delay	INHx/INLx transition to GHx/GLx transition		200		ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)	FOUR-LEVEL H/W INPUTS (GAIN, MODE)
V I1	Input mode 1 voltage	Tied to GND		0		V
V I2	Input mode 2 voltage	47 k Ω ± 5% to tied GND		1.9		V
V I3	Input mode 3 voltage	Hi-Z		3.1		V
V I4	Input mode 4 voltage	Tied to DVDD		5		V
R PU	Pullup resistance	Internal pullup to DVDD		50		k Ω
R PD	Pulldown resistance	Internal pulldown to GND		84		k Ω
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)	SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
V I1	Input mode 1 voltage	Tied to GND		0		V
V I2	Input mode 2 voltage	18 k Ω ± 5% tied to GND		0.8		V
V I3	Input mode 3 voltage	75 k Ω ± 5% tied to GND		1.7		V
V I4	Input mode 4 voltage	Hi-Z		2.5		V
V I5	Input mode 5 voltage	75 k Ω ± 5% tied to DVDD		3.3		V
V I6	Input mode 6 voltage	18 k Ω ± 5% tied to DVDD		4.2		V
V I7	Input mode 7 voltage	Tied to DVDD		5		V
R PU	Pullup resistance	Internal pullup to DVDD		73		k Ω
R PD	Pulldown resistance	Internal pulldown to GND		73		k Ω
OPEN DRAIN OUTPUTS (nFAULT, SDO)	OPEN DRAIN OUTPUTS (nFAULT, SDO)
V OL	Output logic low voltage	I O = 5 mA			0.125	V
I OZ	Output high impedance leakage	V O = 5 V	-2		2	μA

at TA = -40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)	GATE DRIVERS (GHx, GLx)
		V VM = 15 V, I VCP = 0 to 25 mA	9	10.5	12	V
	High-side	V VM = 12 , I VCP = 0 to 20 mA	7.5	10	11.5	V
	V GSH with respect	V VM = 10 V, I VCP = 0 to 15 mA	6	8	9.5	V
		V VM = 9 V, I VCP = 0 to 10 mA	5.5	7.5	8.5	V
		V VM = 15 V, I VGLS = 0 to 25 mA	9.5	11	12.5
	Low-side	V VM = 12 V, I VGLS = 0 to 20 mA	9	10.5	12	V
	V GSL with respect	V VM = 10 V, I VGLS = 0 to 15 mA	7.5	9	10.5	V
	t DEAD	V VM = 9 V, I VGLS = 0 to 10 mA DEAD_TIME = 00b DEAD_TIME = 01b DEAD_TIME = 10b DEAD_TIME = 11b TDRIVE = 00b TDRIVE = 01b	6.5	8 50 100 200 400 100 500 1000	9.5	V ns
	t DRIVE I DRIVEP	TDRIVE = 10b TDRIVE = 11b IDRIVEP_HS or IDRIVEP_LS = 0000b IDRIVEP_HS or IDRIVEP_LS = 0001b IDRIVEP_HS or IDRIVEP_LS = 0010b IDRIVEP_HS or IDRIVEP_LS = 0011b IDRIVEP_HS or IDRIVEP_LS = 0100b IDRIVEP_HS or IDRIVEP_LS = 0101b IDRIVEP_HS or IDRIVEP_LS = 0110b IDRIVEP_HS or IDRIVEP_LS = 0111b IDRIVEP_HS or IDRIVEP_LS = 1000b IDRIVEP_HS or IDRIVEP_LS = 1001b IDRIVEP_HS or IDRIVEP_LS = 1010b IDRIVEP_HS or IDRIVEP_LS = 1011b IDRIVEP_HS or IDRIVEP_LS = 1101b IDRIVEP_HS or IDRIVEP_LS = 1110b IDRIVEP_HS or IDRIVEP_LS = 1111b IDRIVE = Tied to GND IDRIVE = 18 k Ω ± 5% tied to GND IDRIVE = 75 k Ω ± 5% tied to GND IDRIVE = Hi-Z IDRIVE = 75 k Ω ± 5% tied to DVDD IDRIVE = 18 k Ω ± 5% tied to DVDD		2000 4000 4000 50 50 100 150 300 350 400 450 550 600 650 700 900 950 1000 50 100 150 300 450 700		ns mA

		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I DRIVEN	PARAMETER SPI	IDRIVEN_HS or IDRIVEN_LS = 0000b IDRIVEN_HS or IDRIVEN_LS = 0001b IDRIVEN_HS or IDRIVEN_LS = 0010b IDRIVEN_HS or IDRIVEN_LS = 0011b IDRIVEN_HS or IDRIVEN_LS = 0100b IDRIVEN_HS or IDRIVEN_LS = 0101b IDRIVEN_HS or IDRIVEN_LS = 0110b IDRIVEN_HS or IDRIVEN_LS = 0111b IDRIVEN_HS or IDRIVEN_LS = 1000b IDRIVEN_HS or IDRIVEN_LS = 1001b IDRIVEN_HS or IDRIVEN_LS = 1010b		100 100 200 300 600 700 800 900 1100 1200 1300
	Peak sink gate current H/W	IDRIVEN_HS or IDRIVEN_LS = 1011b IDRIVEN_HS or IDRIVEN_LS = 1100b IDRIVEN_HS or IDRIVEN_LS = 1101b IDRIVEN_HS or IDRIVEN_LS = 1110b IDRIVEN_HS or IDRIVEN_LS = 1111b IDRIVE = Tied to GND IDRIVE = 18 k Ω ± 5% tied to GND IDRIVE = 75 k Ω ± 5% tied to GND IDRIVE = Hi-Z IDRIVE = 75 k Ω ± 5% tied to DVDD IDRIVE = 18 k Ω ± 5% tied to DVDD IDRIVE = Tied to DVDD		1400 1700 1800 1900 2000 100 200 300 600 900 1400 2000		mA
I HOLD	Gate holding current	Source current after t DRIVE Sink current after t DRIVE		50 100		mA
I STRONG	Gate strong pulldown current	GHx to SHx and GLx to SPx/SLx		2		A
R OFF	Gate hold off resistor	GHx to SHx and GLx to SPx/SLx		150		k Ω
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)	CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
G CSA	Amplifier gain	CSA_GAIN = 00b	4.85	5	5.15	V/V
G CSA	Amplifier gain	CSA_GAIN = 01b	9.7	10	10.3	V/V
G CSA	SPI	CSA_GAIN = 10b	19.4	20	20.6	V/V
G CSA	Amplifier gain	CSA_GAIN = 11b	38.8	40	41.2	V/V
G CSA	Amplifier gain	GAIN = Tied to GND	4.85	5	5.15	V/V
G CSA	Amplifier gain	GAIN = 47 k Ω ± 5% tied to GND	9.7	10	10.3	V/V
G CSA	H/W	GAIN = Hi-Z	19.4	20	20.6	V/V
t SET		V O_STEP = 0.5 V, G CSA = 5 V/V		250		ns
t SET		V O_STEP = 0.5 V, G CSA = 10 V/V		500		ns
t SET	Settling time to ±1%	V O_STEP = 0.5 V, G VSA = 20 V/V		1000		ns
t SET		V O_STEP = 0.5 V, G CSA = 40 V/V		2000		ns
V COM	Common mode input range		-0.15		0.15	V
V DIFF	Differential mode input range		-0.3		0.3	V
V OFF	Input offset error	V SP = V SN = 0 V	-3		3	mV
V DRIFT	Drift offset	V SP = V SN = 0 V		10		μV/°C
V LINEAR	SOx output voltage linear range		0.25		V VREF - 0.25	V

at TA = -40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER			TEST CONDITIONS	TYP	MAX	UNIT
V BIAS	SOx output voltage bias	SPI Device H/W Device	V SP = V SN = 0 V, VREF_DIV = 0b V SP = V SN = 0 V, VREF_DIV = 1b V SP = V SN = 0 V	V VREF - 0.3 V VREF / 2 V VREF / 2		V
I BIAS	SPx/SNx input bias current				250	μA
V SLEW	SOx output slew rate		60-pF load	10		V/μs
I VREF	VREF input current		V VREF = 5 V	1.5	2.5	mA
UGB Unity gain	bandwidth		DRV835x: 60-pF load	10		MHz
		DRV835xR:	60-pF load	1		MHz
PROTECTION CIRCUITS
V VM_UV			DRV835x: VM falling, UVLO report DRV835x: VM rising, UVLO recovery	8.3 8.5	8.8 9	V
	VM undervoltage lockout		DRV835xR: VM falling, UVLO report DRV835xR: VM rising, UVLO recovery	8.3 8.5	8.6 8.8
V VM_UVH	VM undervoltage hysteresis		Rising to falling threshold	200		mV
t VM_UVD	VM undervoltage deglitch time		VM falling, UVLO report	10		μs
V VDR_UV			DRV835x: VDRAIN falling, UVLO report DRV835x: VDRAIN rising, UVLO recovery	6.4 6.6	6.8 7	V
	VDRAIN undervoltage lockout		DRV835xR: VDRAIN falling, UVLO report DRV835xR: VDRAIN rising, UVLO recovery	6.4 6.6	6.7 6.9
V VDR_UVH	VDRAIN undervoltage hysteresis		Rising to falling threshold	200		mV
t VDR_UVD	VDRAIN undervoltage deglitch time		VDRAIN falling, UVLO report	10		μs
V VCP_UV	VCP charge pump undervoltage lockout		VCP falling, GDUV report	V DRAIN + 5		V
V VGLS_UV	VGLS low-side regulator undervoltage lockout		VGLS falling, GDUV report	4.25		V
V GS_CLAMP	High-side gate clamp		Positive clamping voltage Negative clamping voltage	13.5 -0.7	16	V

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V VDS_OCP	DRV835x: VDS_LVL = 0000b	0.041	0.06	0.072	V
	DRV835x: VDS_LVL = 0001b	0.051	0.07	0.084
	DRV835x: VDS_LVL = 0010b	0.061	0.08	0.096
	DRV835x: VDS_LVL = 0011b	0.071	0.09	0.108
	DRV835x: VDS_LVL = 0100b	0.081	0.1	0.115
	DRV835xR: VDS_LVL = 0000b	0.048	0.06	0.072
	DRV835xR: VDS_LVL = 0001b	0.056	0.07	0.084
	DRV835xR: VDS_LVL = 0010b	0.064	0.08	0.096
	DRV835xR: VDS_LVL = 0011b	0.072	0.09	0.108
	DRV835xR: VDS_LVL = 0100b	0.085	0.1	0.115
	VDS_LVL = 0101b	0.18	0.2	0.22
	VDS_LVL = 0110b	0.27	0.3	0.33
	VDS_LVL = 0111b	0.36	0.4	0.44
	VDS_LVL = 1000b	0.45	0.5	0.55
	VDS_LVL = 1001b	0.54	0.6	0.66
	VDS_LVL = 1010b	0.63	0.7	0.77
	VDS_LVL = 1011b	0.72	0.8	0.88
	VDS_LVL = 1100b	0.81	0.9	0.99
	VDS_LVL = 1101b	0.9	1.0	1.1
	VDS_LVL = 1110b	1.35	1.5	1.65
	VDS_LVL = 1111b	1.8	2	2.2
	DRV835x: VDS = Tied to GND	0.041	0.06	0.072	V
	DRV835x: VDS = 18 k Ω ± 5% tied to GND	0.081	0.1	0.115	V
	DRV835xR: VDS = Tied to GND	0.048	0.06	0.072	V
	DRV835xR: VDS = 18 k Ω ± 5% tied to GND	0.085	0.1	0.115	V
	VDS = 75 k Ω ± 5% tied to GND	0.18	0.2	0.22	V
	VDS = Hi-Z	0.36	0.4	0.44	V
	VDS = 75 k Ω ± 5% tied to DVDD	0.63	0.7	0.77	V
	VDS = 18 k Ω ± 5% tied to DVDD	0.9	1	1.1	V
	VDS = Tied to DVDD		Disabled		V
t OCP_DEG	OCP_DEG = 00b		1		μs
t OCP_DEG	OCP_DEG = 01b		2		μs
t OCP_DEG	OCP_DEG = 10b		4		μs
t OCP_DEG	OCP_DEG = 11b		8 4		μs
V SEN_OCP	SEN_LVL = 00b		0.25		V
V SEN_OCP	SEN_LVL = 01b		0.5		V
V SEN_OCP	SEN_LVL = 10b		0.75		V
V SEN_OCP	SEN_LVL = 11b		1 1		V
	TRETRY = 0b		8		ms
	TRETRY = 1b		50 8		μ s ms
T OTW	Die temperature, T J	130	150	170	°C
T OTSD	Die temperature, T J	150	170	190	°C
T HYS	Die temperature, T J		20		°C
V VCC_REG		6.6	7	7.4	V
	V VIN = 6 to 8.5 V		100		mV
V VCC_BYT	V VIN increasing		8.5		V

at TA = -40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V VCC_BYH	VCC bypass hysteresis	V VIN = 6 V		300 100		mV Ω
V VCC_OUT	VCC output impedance	V VIN = 10 V V VIN = 48 V		8.8 0.8		Ω Ω
V VCC_LIM	VCC current limit			9.2		mA
V VCC_UV	VCC undervoltage lockout			5.3		V
V VCC_UVH	VCC undervoltage lockout hysteresis			190		mV
V VCC_UVFD	VCC filter delay			3		μ s
I IN_OP	IIN operating current	FB = 3 V		550	750	μ A
I IN_OP	IIN shutdown current	RT/SD = 0 V		110	176	μ A
BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING	BUCK REGULATOR SWITCHING
R DS(on)	Buck switch R DS(on)	I TEST = 200 mA		1.25	2.57	Ω
V GATE_UV	Gate drive undervoltage lockout	V BST - V SW rising	2.8	3.8	4.8	V
V GATE_UVH	Gate drive undervoltage lockout hysteresis			490		mV
V SWITCH	Pre-charge switch voltage	At 1 mA		0.8		V
t ON	Pre-charge switch on-time			150		ns
BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT	BUCK REGULATOR CURRENT LIMIT
I LIMIT	Current limit threshold		0.41	0.51	0.61	A
t LIM	Current limit response time	I SW overdrive = 0.1 A, time to switch off		350		ns
t OFF1	Off time generator	FB = 0 V, RCL = 100 k Ω		35		μ s
t OFF2	Off time generator	FB = 2.3 V, RCL = 100 k Ω		2.56		μ s
BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR	BUCK REGULATOR ON TIME GENERATOR
t ON1	Ton 1	V VIN = 10 V, RON = 200 k Ω	2.15	2.77	3.5	μ s
t ON2	Ton 2	V VIN = 95 V, RON = 200 k Ω	200	300	420	μ s
V SDT	Remote shutdown threshold	Rising	0.4	0.7	1.05	V
V SDH	Remote shutdown hysteresis			35		mV
BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME	BUCK REGULATOR MINIMUM OFF TIME
t OFF_MIN	Minimum off time	FB = 0 V		300		ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS	BUCK REGULATOR REGULATIONS AND OV COMPARATORS
V FB	FB reference threshold	Internal reference, trip point for switch on	2.445	2.5	2.55	V
V FB_OV	FB overvoltage threshold	Trip point for switch off		2.875		V
I FB_BIAS	FB bias current			100		μ A
BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN	BUCK REGULATOR THERMAL SHUTDOWN
T SD	Thermal shutdown threshold			165		°C
T SDH	Thermal shutdown hysteresis			25		°C

Absolute Maximum Ratings

at TA = -40°C to +125°C (unless otherwise noted) (1)

	MIN	MAX	UNIT
GATE DRIVER
Power supply pin voltage (VM)	-0.3	80	V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)	-0.3	0.3	V
MOSFET drain sense pin voltage (VDRAIN)	-0.3	102	V
MOSFET drain sense pin voltage slew rate (VDRAIN)	0	2	V/μs
Charge pump pin voltage (CPH, VCP)	-0.3	V VDRAIN + 16	V
Charge-pump negative-switching pin voltage (CPL)	-0.3	V VDRAIN	V
Low-side gate drive regulator pin voltage (VGLS)	-0.3	18	V
Internal logic regulator pin voltage (DVDD)	-0.3	5.75	V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS)	-0.3	5.75	V
Continuous high-side gate drive pin voltage (GHx)	-5 (2)	V VCP + 0.3	V
Transient 200-ns high-side gate drive pin voltage (GHx)	-10	V VCP + 0.3	V
High-side gate drive pin voltage with respect to SHx (GHx)	-0.3	16	V
Continuous high-side source sense pin voltage (SHx)	-5 (2)	102	V
Continuous high-side source sense pin voltage (SHx)	-5 (2)	V VDRAIN + 5	V
Transient 200-ns high-side source sense pin voltage (SHx)	-10	V VDRAIN + 10	V
Continuous low-side gate drive pin voltage (GLx)	-1.0	V VGLS + 0.3	V
Transient 200-ns low-side gate drive pin voltage (GLx)	-5.0	V VGLS + 0.3	V
Gate drive pin source current (GHx, GLx)	Internally limited	Internally limited	A
Gate drive pin sink current (GHx, GLx)	Internally limited	Internally limited	A
Continuous low-side source sense pin voltage (SLx)	-1	1	V
Transient 200-ns low-side source sense pin voltage (SLx)	-5	5	V
Continuous shunt amplifier input pin voltage (SNx, SPx)	-1	1	V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)	-5	5	V
Reference input pin voltage (VREF)	-0.3	5.75	V
Shunt amplifier output pin voltage (SOx)	-0.3	V VREF + 0.3	V
BUCK REGULATOR
Power supply pin voltage (VIN)	-0.3	100	V
Bootstrap pin voltage (BST)	-0.3	114	V
Bootstrap pin voltage with respect to SW (BST)	-0.3	14	V
Bootstrap pin voltage with respect to VCC (BST)	-0.3	100	V
Switching node pin voltage (SW)	-1	V VIN	V
Internal regulator pin voltage (VCC)	-0.3	14	V
Input pin voltage (FB, RCL, RT/SD)	-0.3	7	V
DRV835x
Ambient temperature, T A	-40	125	°C
Junction temperature, T J	-40	150	°C
Storage temperature, T stg	-65	150	°C

Recommended Operating Conditions

at TA = -40°C to +125°C (unless otherwise noted)

		MIN	MAX	UNIT
GATE DRIVER	GATE DRIVER
V VM	Gate driver power supply voltage (VM)	9	75	V
V VDRAIN	Charge pump reference and drain voltage sense (VDRAIN)	7	100	V
V I	Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)	0	5.5	V
f PWM	Applied PWM signal (INHx, INLx)	0	200 (1)	kHz
t SH	Switch-node slew rate range (SHx)	0	2	V/ns
I GATE_HS	High-side average gate-drive current (GHx)	0	25 (1)	mA
I GATE_LS	Low-side average gate-drive current (GLx)	0	25 (1)	mA
I DVDD	External load current (DVDD)	0	10 (1)	mA
V VREF	Reference voltage input (VREF)	3	5.5	V
I SO	Shunt amplifier output current (SOx)	0	5	mA
V OD	Open drain pullup voltage (nFAULT, SDO)	0	5.5	V
I OD	Open drain output current (nFAULT, SDO)	0	5	mA
BUCK REGULATOR	BUCK REGULATOR
V VIN	Power supply voltage (VIN)	6	95	V
DRV835x	DRV835x
T A	Operating ambient temperature	-40	125	°C
T J	Operating junction temperature	-40	150	°C

Thermal Information

Not to scale

Typical Application

The DRV835x family of devices are primarily used in three-phase brushless DC motor control applications. The design procedures in the Typical Application section highlight how to use and configure the DRV835x family of devices.

Package Information

PLASTIC QUAD FLATPACK - NO LEAD

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
DRV8350	Texas Instruments	—
DRV8350R	Texas Instruments	—
DRV8353	Texas Instruments	—
DRV8353H	Texas Instruments	—
DRV8353HRTAR	Texas Instruments	—
DRV8353HRTAT	Texas Instruments	—
DRV8353R	Texas Instruments	—
DRV8353RH	Texas Instruments	—
DRV8353RS	Texas Instruments	VQFN-48 (RGZ)
DRV8353RX	Texas Instruments	VQFN-48 (7
DRV8353S	Texas Instruments	—
DRV8353SRTAR	Texas Instruments	—
DRV8353SRTAT	Texas Instruments	—
DRV8353X	Texas Instruments	—
DRV8353XS	Texas Instruments	—
DRV835X	Texas Instruments	—

Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.

Get structured datasheet data via API

Get started free