DRV8353X

[DRV8350](http://www.ti.com/product/drv8350?qgpn=drv8350), [DRV8350R](http://www.ti.com/product/drv8350r?qgpn=drv8350r) [DRV8353](http://www.ti.com/product/drv8353?qgpn=drv8353), [DRV8353R](http://www.ti.com/product/drv8353r?qgpn=drv8353r)

Manufacturer

Texas Instruments

Category

Integrated Circuits (ICs)

Overview

Part: DRV835x from Texas Instruments

Type: 100-V Three-Phase Smart Gate Driver

Key Specs:

  • Triple half-bridge gate driver voltage range: 9 to 100-V
  • Buck regulator operating voltage range: 6 to 95-V
  • Buck regulator output capability: 2.5 to 75-V, 350-mA
  • Peak source current: 50-mA to 1-A
  • Peak sink current: 100-mA to 2-A
  • Current shunt amplifier adjustable gain: 5, 10, 20, 40 V/V
  • Low-power sleep mode current: 20 μA at VVM = 48-V

Features:

  • Triple half-bridge gate driver
  • Optional integrated buck regulator
  • Optional triple low-side current shunt amplifiers
  • Smart gate drive architecture
  • Adjustable slew rate control for EMI performance
  • VGS handshake and minimum dead-time insertion to prevent shoot-through
  • dV/dt mitigation through strong pulldown
  • Integrated gate driver power supplies
  • High-side doubler charge pump For 100% PWM duty cycle control
  • Low-side linear regulator
  • Integrated LM5008A buck regulator
  • Integrated triple current shunt amplifiers
  • Bidirectional or unidirectional support
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 120° sensored operation
  • SPI or hardware interface available
  • Low-power sleep mode
  • Integrated protection features (VM undervoltage lockout (UVLO), Gate drive supply undervoltage (GDUV), MOSFET VDS overcurrent protection (OCP), MOSFET shoot-through prevention, Gate driver fault (GDF), Thermal warning and shutdown (OTW/OTSD), Fault condition indicator (nFAULT))

Applications:

  • 3-phase brushless-DC (BLDC) motor modules
  • Fans, blowers, and pumps
  • E-Bikes, E-scooters, and E-mobility
  • Power and garden tools, lawn mowers
  • Drones, robotics, and RC toys
  • Factory automation and textile machines

Package:

  • DRV8350: WQFN (32), 5.00 mm × 5.00 mm
  • DRV8350R: VQFN (48), 7.00 mm × 7.00 mm
  • DRV8353: WQFN (40), 6.00 mm × 6.00 mm
  • DRV8353R: VQFN (48), 7.00 mm × 7.00 mm

Features

  • 1 9 to 100-V, Triple half-bridge gate driver
    • Optional integrated buck regulator
    • Optional triple low-side current shunt amplifiers
  • Smart gate drive architecture
    • Adjustable slew rate control for EMI performance
    • VGS handshake and minimum dead-time insertion to prevent shoot-through
    • 50-mA to 1-A peak source current
    • 100-mA to 2-A peak sink current
    • dV/dt mitigation through strong pulldown
  • Integrated gate driver power supplies
    • High-side doubler charge pump For 100% PWM duty cycle control
    • Low-side linear regulator
  • Integrated LM5008A buck regulator
    • 6 to 95-V operating voltage range
    • 2.5 to 75-V, 350-mA output capability
  • Integrated triple current shunt amplifiers
    • Adjustable gain (5, 10, 20, 40 V/V)
  • Bidirectional or unidirectional support
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 120° sensored operation
  • SPI or hardware interface available
  • Low-power sleep mode (20 μA at VVM = 48-V)
  • • Integrated protection features
    • VM undervoltage lockout (UVLO)
    • Gate drive supply undervoltage (GDUV)
    • MOSFET VDS overcurrent protection (OCP)
    • MOSFET shoot-through prevention
    • Gate driver fault (GDF)
    • Thermal warning and shutdown (OTW/OTSD)
    • Fault condition indicator (nFAULT)

Applications

  • 3-phase brushless-DC (BLDC) motor modules
  • Fans, blowers, and pumps
  • E-Bikes, E-scooters, and E-mobility
  • Power and garden tools, lawn mowers
  • Drones, robotics, and RC toys
  • Factory automation and textile machines

Pin Configuration

Pin Functions—32-Pin DRV8350 Devices

  • NAME
  • CPH
  • CPL
  • DVDD
  • ENABLE
  • GHA
  • GHB
  • GHC
  • GLA
  • GLB

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback

SLVSDY6A –AUGUST 2018–REVISED JUNE 2019 www.ti.com

Pin Functions—32-Pin DRV8350 Devices (continued)

NAMEDRV8350RHDRV8350RSTYPE(1)DESCRIPTION
AGND2727PWRDevice analog ground. Connect to system ground.
BST4545PWRBuck regulator bootstrap input. Connect a X5R or X7R, 0.01-μF, 16-V, capacitor between the BST and SW pins.
CPH44PWRCharge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL33PWRCharge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DGND4141PWRDevice digital ground. Connect to system ground.
DVDD4040PWR5-V internal regulator output. Connect a X5R or X7R, 1-μF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally.
ENABLE3333IGate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-μs low pulse can be used to reset fault conditions.
FB4848OBuck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA88OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB1717OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC1818OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA1010OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB1515OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC2020OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND11PWRDevice primary ground. Connect to system ground.
IDRIVE30IGate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA3434IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB3636IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC3838IHigh-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA3535ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB3737ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC3939ILow-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE29IPWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC1212NCNo internal connection. This pin can be left floating or connected to system ground.
NC1313NCNo internal connection. This pin can be left floating or connected to system ground.
NC2222NCNo internal connection. This pin can be left floating or connected

DRV8350RH RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

DRV8350RS RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

4

Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

DRV8350, DRV8350R DRV8353, DRV8353R

www.ti.com SLVSDY6A –AUGUST 2018–REVISED JUNE 2019

Electrical Characteristics

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVMVM operating supply currentVVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V8.513mA
IVDRAINVDRAIN operating supply current
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V		ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C1.9
20		4
40		mA
ISLEEPSleep mode supply currentENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C100μA
tRSTReset pulse timeENABLE = 0 V period to reset faults540μs
tWAKETurnon timeVVM > VUVLO, ENABLE = 3.3 V to outputs ready1ms
tSLEEPTurnoff timeENABLE = 0 V to device sleep mode1ms
VDVDDDVDD regulator voltageIDVDD = 0 to 10 mA4.7555.25V
VVM = 15 V, IVCP = 0 to 25 mA910.512
VCP operating voltageVVM = 12 V, IVCP = 0 to 20 mA7.51011.5
VVCPwith respect to VDRAINVVM = 10 V, IVCP = 0 to 15 mA689.5V
VVM = 9 V, IVCP = 0 to 10 mA5.57.58.5
VVM = 15 V, IVGLS = 0 to 25 mA1314.516
VGLS operating voltageVVM = 12 V, IVGLS = 0 to 20 mA1011.512.5
VVGLSwith respect to GNDVVM = 10 V, IVGLS = 0 to 15 mA89.510.5V
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)VVM = 9 V, IVGLS = 0 to 10 mA78.59.5
VILInput logic low voltage00.8V
VIHInput logic high voltage1.55.5V
VHYSInput logic hysteresis100mV
IILInput logic low currentVVIN = 0 V–55μA
IIHInput logic high currentVVIN = 5 V5070μA
RPDPulldown resistanceTo GND100kΩ
tPDPropagation delay
FOUR-LEVEL H/W INPUTS (GAIN, MODE)		INHx/INLx transition to GHx/GLx transition200ns
VI1Input mode 1 voltageTied to GND0V
VI2Input mode 2 voltage47 kΩ ± 5% to tied GND1.9V
VI3Input mode 3 voltageHi-Z3.1V
VI4Input mode 4 voltageTied to DVDD5V
RPUPullup resistanceInternal pullup to DVDD50kΩ
RPDPulldown resistanceInternal pulldown to GND84kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1Input mode 1 voltageTied to GND0V
VI2Input mode 2 voltage18 kΩ ± 5% tied to GND0.8V
VI3Input mode 3 voltage75 kΩ ± 5% tied to GND1.7V
VI4Input mode 4 voltageHi-Z2.5V
VI5Input mode 5 voltage75 kΩ ± 5% tied to DVDD
3.3		V
VI6Input mode 6 voltage18 kΩ ± 5% tied to DVDD4.2V
VI7Input mode 7 voltageTied to DVDD5V
RPUPullup resistanceInternal pullup to DVDD73kΩ
RPDPulldown resistanceInternal pulldown to GND73kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOLOutput logic low voltageIO = 5 mA0.125V
IOZOutput high impedance leakageVO = 5 V–22μA
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IDRIVENPeak sink gate currentSPI DeviceIDRIVEN_HS or IDRIVEN_LS = 0000b100
IDRIVENPeak sink gate currentSPI DeviceIDRIVEN_HS or IDRIVEN_LS = 0001b100
IDRIVENPeak sink gate currentSPI DeviceIDRIVEN_HS or IDRIVEN_LS = 0010b200
IDRIVENPeak sink gate currentSPI Device
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SPI DeviceIDRIVEN_HS or IDRIVEN_LS = 0000b
IDRIVEN_HS or IDRIVEN_LS = 0001b
IDRIVEN_HS or IDRIVEN_LS = 0010b
IDRIVEN_HS or IDRIVEN_LS = 0011b
IDRIVEN_HS or IDRIVEN_LS = 0100b
IDRIVEN_HS or IDRIVEN_LS = 0101b
IDRIVEN_HS or IDRIVEN_LS = 0110b
IDRIVEN_HS or IDRIVEN_LS = 0111b
IDRIVEN_HS or IDRIVEN_LS = 1000b
IDRIVEN_HS or IDRIVEN_LS = 1001b
IDRIVEN_HS or IDRIVEN_LS = 1010b		100
100
200
300
600
700
800
900
1100
1200
1300
IDRIVENPeak sink
gate current
IHOLD
Gate holding current		H/W DeviceIDRIVEN_HS or IDRIVEN_LS = 1011b
IDRIVEN_HS or IDRIVEN_LS = 1100b
IDRIVEN_HS or IDRIVEN_LS = 1101b
IDRIVEN_HS or IDRIVEN_LS = 1110b
IDRIVEN_HS or IDRIVEN_LS = 1111b
IDRIVE = Tied to GND
IDRIVE = 18 kΩ ± 5% tied to GND
IDRIVE = 75 kΩ ± 5% tied to GND
IDRIVE = Hi-Z
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
Source current after tDRIVE
Sink current after tDRIVE		300
900
1400
2000		1400
1700
1800
1900
2000
100
200
600
50
100		mA
mA
ISTRONGGate strong pulldown currentGHx to SHx and GLx to SPx/SLx2A
ROFFGate hold off resistorGHx to SHx and GLx to SPx/SLx150kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
SPI DeviceCSA_GAIN = 00b4.8555.15
CSA_GAIN = 01b9.71010.3
CSA_GAIN = 10b19.42020.6
CSA_GAIN = 11b38.84041.2
GCSAAmplifier gainGAIN = Tied to GND4.8555.15V/V
GAIN = 47 kΩ ± 5% tied to GND9.71010.3
H/W DeviceGAIN = Hi-Z19.42020.6
GAIN = Tied to DVDD
VO_STEP = 0.5 V, GCSA = 5 V/V		38.840
250		41.2
tSETVO_STEP = 0.5 V, GCSA = 10 V/V500
Settling time to ±1%VO_STEP = 0.5 V, GVSA = 20 V/V
VO_STEP = 0.5 V, GCSA = 40 V/V		1000
2000		ns
VCOMCommon mode input range–0.150.15V
VDIFFDifferential mode input range–0.30.3V
VOFFInput offset errorVSP = VSN = 0 V–33mV
VDRIFTDrift offsetVSP = VSN = 0 V10μV/°C
VLINEARSOx output voltage linear range0.25VVREF –
0.25		V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VVDS_OCPVDS overcurrent trip voltageDRV835x: VDS_LVL = 0000b0.0410.060.072
VVDS_OCPVDS overcurrent trip voltageDRV835x: VDS_LVL = 0001b0.0510.070.084
VVDS_OCPVDS overcurrent trip voltageDRV835x: VDS_LVL = 0010b0.0610.080.096
VVDS_OCPVDS overcurrent trip voltageDRV835x: VDS_LVL = 0011b0.0710.090.108
VVDS_OCPVDS overcurrent trip voltageDRV835x: VDS_LVL = 0100b0.0810.10.115
VVDS_OCPVDS overcurrent trip voltageSPI DeviceDRV835xR: VDS_LVL = 0000b0.0480.06
VVDS_OCPVDS overcurrent trip voltageSPI DeviceDRV835xR: VDS_LVL = 0001b0.0560.07
VVDS_OCPVDS overcurrent trip voltageSPI DeviceDRV835xR: VDS_LVL = 0010b0.0640.08
VVDS_OCPVDS overcurrent trip voltageSPI DeviceDRV835xR: VDS_LVL = 0011b0.0720.09
VVDS_OCPVDS overcurrent trip voltageSPI DeviceDRV835xR: VDS_LVL = 0100b0.0850.1
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 0101b0.180.2
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 0110b0.270.3
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 0111b0.360.4
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1000b0.450.5
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1001b0.540.6
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1010b0.630.7
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1011b0.720.8
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1100b0.810.9
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1101b0.91.0
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1110b1.351.5
VVDS_OCPVDS overcurrent trip voltageSPI DeviceVDS_LVL = 1111b1.82
VVDS_OCPVDS overcurrent trip voltageH/W DeviceDRV835x: VDS = Tied to GND0.0410.06
VVDS_OCPVDS overcurrent trip voltageH/W DeviceDRV835x: VDS = 18 kΩ ± 5% tied to GND0.0810.1
VVDS_OCPVDS overcurrent trip voltageH/W DeviceDRV835xR: VDS = Tied to GND0.0480.06
VVDS_OCPVDS overcurrent trip voltageH/W DeviceDRV835xR: VDS = 18 kΩ ± 5% tied to GND0.0850.1
VVDS_OCPVDS overcurrent trip voltageH/W DeviceVDS = 75 kΩ ± 5% tied to GND0.180.2
VVDS_OCPVDS overcurrent trip voltageH/W DeviceVDS = Hi-Z0.360.4
VVDS_OCPVDS overcurrent trip voltageH/W DeviceVDS = 75 kΩ ± 5% tied to DVDD0.630.7
VVDS_OCPVDS overcurrent trip voltageH/W DeviceVDS = 18 kΩ ± 5% tied to DVDD0.91
VVDS_OCPVDS overcurrent trip voltageH/W DeviceVDS = Tied to DVDDDisabled
tOCP_DEGVDS and VSENSE overcurrent deglitch timeSPI DeviceOCP_DEG = 00b1
tOCP_DEGVDS and VSENSE overcurrent deglitch timeSPI DeviceOCP_DEG = 01b2
tOCP_DEGVDS and VSENSE overcurrent deglitch timeSPI DeviceOCP_DEG = 10b4
tOCP_DEGVDS and VSENSE overcurrent deglitch timeSPI DeviceOCP_DEG = 11b8
tOCP_DEGVDS and VSENSE overcurrent deglitch timeH/W Device4
VSEN_OCPVSENSE overcurrent trip voltageSPI DeviceSEN_LVL = 00b0.25
VSEN_OCPVSENSE overcurrent trip voltageSPI DeviceSEN_LVL = 01b0.5
VSEN_OCPVSENSE overcurrent trip voltageSPI DeviceSEN_LVL = 10b0.75
VSEN_OCPVSENSE overcurrent trip voltageSPI DeviceSEN_LVL = 11b1
VSEN_OCPVSENSE overcurrent trip voltageH/W Device1
tRETRYOvercurrent retry timeSPI DeviceTRETRY = 0b8
tRETRYOvercurrent retry timeSPI DeviceTRETRY = 1b50
tRETRYOvercurrent retry timeH/W Device8
TOTWThermal warning temperatureDie temperature, TJ130150170
TOTSDThermal shutdown temperatureDie temperature, TJ150170190
THYSThermal hysteresisDie temperature, TJ20
BUCK REGULATOR VCC
VVCC_REGVCC regulator voltageVVIN = 6 to 8.5 V6.677.4
VVCC_BTTVCC bypass thresholdVVIN Increasing8.5

at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VCC_BYHVCC bypass hysteresis300mV
VCC_OUTVCC output impedanceVIN = 6 V100
VCC_OUTVCC output impedanceVIN = 10 V8.8
VCC_OUTVCC output impedanceVIN = 48 V0.8
VCC_LIMVCC current limit9.2
VCC_UVVCC undervoltage lockout5.3
VCC_UVHVCC undervoltage lockout hysteresis190
VCC_UVFDVCC filter delay3
IIN_OPIIN operating currentFB = 3 V550750
IIN_OPIIN shutdown currentRT/SD = 0 V110176
BUCK REGULATOR SWITCHING
RDS(on)Buck switch RDS(on)ITEST = 200 mA1.252.57
VGATE_UVGate drive undervoltage lockoutVBST - VSW rising2.83.84.8
VGATE_UVHGate drive undervoltage lockout hysteresis490
VSWITCHPre-charge switch voltageAt 1 mA0.8
tONPre-charge switch on-time150
BUCK REGULATOR CURRENT LIMIT
ILIMITCurrent limit threshold0.410.510.61A
tLIMCurrent limit response timeISW overdrive = 0.1 A, time to switch off350
tOFF1Off time generatorFB = 0 V, RCL = 100 kΩ35
tOFF2Off time generatorFB = 2.3 V, RCL = 100 kΩ2.56
BUCK REGULATOR ON TIME GENERATOR
tON1Ton 1VIN = 10 V, RON = 200 kΩ2.152.773.5
tON2Ton 2VIN = 95 V, RON = 200 kΩ200300420
VSDTRemote shutdown thresholdRising0.40.71.05
VSDHRemote shutdown hysteresis35
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MINMinimum off timeFB = 0 V300
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFBFB reference thresholdInternal reference, trip point for switch on2.4452.52.55
VFB_OVFB overvoltage thresholdTrip point for switch off2.875
IFB_BIASFB bias current100
BUCK REGULATOR THERMAL SHUTDOWN
TSDThermal shutdown threshold165
TSDHThermal shutdown hysteresis25

MINNOMMAXUNIT
tREADYSPI ready after enableVM > UVLO, ENABLE = 3.3 V1ms
tCLKSCLK minimum period100ns
tCLKHSCLK minimum high time50ns
tCLKLSCLK minimum low time50ns
tSU_SDISDI input data setup time20ns
tH_SDISDI input data hold time30ns
tD_SDOSDO output data delay timeSCLK high to SDO valid30ns
tSU_nSCSnSCS input setup time50ns
tH_nSCSnSCS input hold time50ns
tH_nSCSnSCS minimum high time before active low400ns
tDIS_nSCSnSCS disable timenSCS high to SDO high impedance10ns

DRV8350, DRV8350R DRV8353, DRV8353R

SLVSDY6A –AUGUST 2018–REVISED JUNE 2019 www.ti.com

7.6 SPI Timing Requirements

at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)

INLxINHxGLxGHxSHx
00LLHi-Z
01LHH
10HLL
11LLHi-Z

Figure 1. SPI Slave Mode Timing Diagram

Absolute Maximum Ratings

at TA = –40°C to +125°C (unless otherwise noted)(1)

MINMAXUNIT
GATE DRIVER
Power supply pin voltage (VM)–0.380V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)–0.30.3V
MOSFET drain sense pin voltage (VDRAIN)–0.3102V
MOSFET drain sense pin voltage slew rate (VDRAIN)02V/μs
Charge pump pin voltage (CPH, VCP)–0.3VVDRAIN + 16V
Charge-pump negative-switching pin voltage (CPL)–0.3VVDRAINV
Low-side gate drive regulator pin voltage (VGLS)–0.318V
Internal logic regulator pin voltage (DVDD)–0.35.75V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,
VDS)		–0.35.75V
Continuous high-side gate drive pin voltage (GHx)(2)
–5		VVCP + 0.3V
Transient 200-ns high-side gate drive pin voltage (GHx)–10VVCP + 0.3V
High-side gate drive pin voltage with respect to SHx (GHx)–0.316V
Continuous high-side source sense pin voltage (SHx)(2)
–5		102V
Continuous high-side source sense pin voltage (SHx)(2)
–5		VVDRAIN + 5V
Transient 200-ns high-side source sense pin voltage (SHx)–10VVDRAIN + 10V
Continuous low-side gate drive pin voltage (GLx)–1.0VVGLS + 0.3V
Transient 200-ns low-side gate drive pin voltage (GLx)–5.0VVGLS + 0.3V
Gate drive pin source current (GHx, GLx)Internally limitedInternally limitedA
Gate drive pin sink current (GHx, GLx)Internally limitedInternally limitedA
Continuous low-side source sense pin voltage (SLx)–11V
Transient 200-ns low-side source sense pin voltage (SLx)–55V
Continuous shunt amplifier input pin voltage (SNx, SPx)–11V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)–55V
Reference input pin voltage (VREF)–0.35.75V
Shunt amplifier output pin voltage (SOx)–0.3VVREF + 0.3V
BUCK REGULATOR
Power supply pin voltage (VIN)–0.3100V
Bootstrap pin voltage (BST)–0.3114V
Bootstrap pin voltage with respect to SW (BST)–0.314V
Bootstrap pin voltage with respect to VCC (BST)–0.3100V
Switching node pin voltage (SW)–1VVINV
Internal regulator pin voltage (VCC)–0.314V
Input pin voltage (FB, RCL, RT/SD)–0.37V
DRV835x
Ambient temperature, TA–40125°C
Junction temperature, TJ–40150°C
Storage temperature, Tstg–65150°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum. This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

www.ti.com SLVSDY6A –AUGUST 2018–REVISED JUNE 2019

Recommended Operating Conditions

at TA = –40°C to +125°C (unless otherwise noted)

| THERMAL METRIC(1) | | DRV8350 | DRV8353 | DRV835xR | UNIT | | | | RTV (WQFN) | RTA (WQFN) | RGZ (VQFN) | |

32 PINS40 PINS48 PINS
R_JAJunction-to-ambient thermal resistance29.226.124.7°C/W
R_JC(top)Junction-to-case (top) thermal resistance15.213.112.0°C/W
R_JBJunction-to-board thermal resistance9.28.47.1°C/W
Ψ_JTJunction-to-top characterization parameter0.10.10.1°C/W
Ψ_JBJunction-to-board characterization parameter9.28.47.1°C/W
R_JC(bot)Junction-to-case (bottom) thermal resistance1.21.10.8°C/W

Thermal Information

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
DRV8350HTexas Instruments—
DRV8350RHTexas Instruments—
DRV8350RSTexas Instruments—
DRV8350STexas Instruments—
DRV8353Texas Instruments—
DRV8353HTexas Instruments—
DRV8353HRTARTexas Instruments—
DRV8353HRTAR.ATexas Instruments—
DRV8353HRTATTexas Instruments—
DRV8353HRTAT.ATexas Instruments—
DRV8353RTexas Instruments—
DRV8353RHTexas Instruments—
DRV8353RSTexas Instruments—
DRV8353RSRGZRTexas Instruments48-VFQFN Exposed Pad
DRV8353RXTexas Instruments—
DRV8353STexas Instruments—
DRV8353SRTARTexas Instruments—
DRV8353SRTAR.ATexas Instruments—
DRV8353SRTATTexas Instruments—
DRV8353SRTAT.ATexas Instruments—
DRV8353XSTexas Instruments—
DRV835XTexas Instruments—
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