DRV8350

Part: DRV8350, DRV8350R, DRV8353, DRV8353R from Texas Instruments

Type: Three-Phase Smart Gate Driver

Description: The DRV835x family is a highly-integrated 9–100 V three-phase smart gate driver for BLDC motor applications, featuring adjustable slew rate control, integrated protection, and optional integrated buck regulator (up to 350 mA) and triple current shunt amplifiers.

Operating Conditions:

• Supply voltage (VM): 9–75 V
• Operating temperature: -40 to 125 °C
• PWM signal frequency: 0–200 kHz
• Charge pump reference and drain voltage sense (VDRAIN): 7–100 V

Absolute Maximum Ratings:

• Max supply voltage (VM): 80 V
• Max MOSFET drain sense pin voltage (VDRAIN): 102 V
• Max junction temperature: 150 °C
• Max storage temperature: 150 °C

Key Specs:

• VM operating supply current: 8.5 mA (Typ, VVM = VVDRAIN = 48 V, ENABLE = 3.3 V)
• Sleep mode supply current: 20 µA (Typ, ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C)
• DVDD regulator voltage: 4.75–5.25 V (IDVDD = 0 to 10 mA)
• VCP operating voltage with respect to VDRAIN: 5.5–9.5 V (depending on VVM and IVCP)
• VGLS operating voltage with respect to GND: 7–16 V (depending on VVM and IVGLS)
• Input logic high voltage (VIH): 1.5–5.5 V
• Buck regulator output capability: 2.5–75 V, 350 mA (for 'R' variants)
• Shunt amplifier adjustable gain: 5, 10, 20, 40 V/V (for DRV8353 variants)

Features:

• Smart gate drive architecture with adjustable slew rate control
• VGS handshake and minimum dead-time insertion
• Integrated gate driver power supplies (high-side doubler charge pump, low-side linear regulator)
• Multiple PWM control modes (6x, 3x, 1x, and independent)
• Integrated protection features (UVLO, GDUV, OCP, shoot-through prevention, thermal warning/shutdown)
• Low-power sleep mode

Applications:

• 3-phase brushless-DC (BLDC) motor modules
• Fans, blowers, and pumps
• E-Bikes, E-scooters, and E-mobility
• Power and garden tools, lawn mowers

Package:

• WQFN (32)
• VQFN (48)
• WQFN (40)

• 9 to 100-V, Triple half-bridge gate driver
  • Optional integrated buck regulator
  • Optional triple low-side current shunt amplifiers
• Smart gate drive architecture
  • Adjustable slew rate control for EMI performance
  • V_GS handshake and minimum dead-time insertion to prevent shoot-through
  • 50-mA to 1-A peak source current
  • 100-mA to 2-A peak sink current
  • dV/dt mitigation through strong pulldown
• Integrated gate driver power supplies
  • High-side doubler charge pump For 100% PWM duty cycle control
  • Low-side linear regulator
• Integrated LM5008A buck regulator
  • 6 to 95-V operating voltage range
  • 2.5 to 75-V, 350-mA output capability
• Integrated triple current shunt amplifiers
  • Adjustable gain (5, 10, 20, 40 V/V)
  • Bidirectional or unidirectional support
• 6x, 3x, 1x, and independent PWM modes
  • Supports 120° sensored operation
• SPI or hardware interface available
• Low-power sleep mode (20 μ A at V_VM = 48-V )
• Integrated protection features
  • VM undervoltage lockout (UVLO)
  • Gate drive supply undervoltage (GDUV)
  • MOSFET V_DS overcurrent protection (OCP)
  • MOSFET shoot-through prevention
  • Gate driver fault (GDF)
  • Thermal warning and shutdown (OTW/OTSD)
  • Fault condition indicator (nFAULT)

• 3-phase brushless-DC (BLDC) motor modules
• Fans, blowers, and pumps
• E-Bikes, E-scooters, and E-mobility
• Power and garden tools, lawn mowers
• Drones, robotics, and RC toys
• Factory automation and textile machines

3 Description

The DRV835x family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. These applications include fieldoriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes and a buck regulator to power the gate driver or external controller.

The DRV835x uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events

Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.

Device Information⁽¹⁾

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

Table of Contents

Pin Functions—32-Pin DRV8350 Devices

Pin Functions—32-Pin DRV8350 Devices (continued)

• NAME
• NAME
• GLC
• GND
• IDRIVE
• INHA
• INHB
• INHC
• INLA
• INLB
• INLC
• MODE
• NC
• nFAULT
• nSCS
• SCLK
• SDI
• SDO
• SHA
• SHB
• SHC
• SLA
• SLB
• SLC
• VCP
• VDRAIN
• VDS
• VGLS
• VM

DRV8350RH RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

DRV8350RS RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

Pin Functions—48-Pin DRV8350R Devices

Pin Functions—48-Pin DRV8350R Devices (continued)

DRV8353H RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View

DRV8353S RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View

Pin Functions—40-Pin DRV8353 Devices

• NAME
• NAME
• AGND
• CPH
• CPL
• DVDD
• ENABLE
• GAIN
• GND
• GHA
• GHB
• GHC
• GLA
• GLB
• GLC
• IDRIVE
• INHA
• INHB
• INHC

PWR = power, I = input, O = output, NC = no connection, OD = open-drain

Pin Functions—40-Pin DRV8353 Devices (continued)

• NO.
• NAME
• INLA
• INLB
• INLC
• MODE
• nFAULT
• nSCS
• SCLK
• SDI
• SDO
• SHA
• SHB
• SHC
• SNA
• SNB
• SNC
• SOA
• SOB
• SOC
• SPA
• SPB
• SPC
• VCP
• VDRAIN
• VDS
• VGLS
• VM
• VREF

DRV8353RH RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

DRV8353RS RGZ Package 48-Pin VQFN With Exposed Thermal Pad Top View

Pin Functions—48-Pin DRV8353R Devices

Pin Functions—48-Pin DRV8353R Devices (continued)

7.6 SPI Timing Requirements

at T^A = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)

Figure 1. SPI Slave Mode Timing Diagram

7.7 Typical Characteristics

Typical Characteristics (continued)

8 Detailed Description

8.1 Overview

The DRV835x family of devices are integrated 100-V gate drivers for three-phase motor drive applications. These devices decrease system component count, cost, and complexity by integrating three independent halfbridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages, optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The lowside gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.

The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture, VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent monitor reference.

The DRV8353 and DRV8353R devices integrate three, bidirectional current-shunt amplifiers for monitoring the current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility to adjust the output bias point.

The DRV8350R and DRV8353R devices integrate a 350-mA buck regulator that can be used to power an external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can use either the same or a different power supply from the gate driver.

In addition to the high level of device integration, the DRV835x family of devices provides a wide range of integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.

The DRV835x family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN sizes are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin package.

8.2 Functional Block Diagram

Figure 14. Block Diagram for DRV8350H

Figure 15. Block Diagram for DRV8350S

Figure 16. Block Diagram for DRV8350RH

Figure 17. Block Diagram for DRV8350RS

Figure 18. Block Diagram for DRV8353H

Figure 19. Block Diagram for DRV8353S

Figure 20. Block Diagram for DRV8353RH

Figure 21. Block Diagram for DRV8353RS

8.3 Feature Description

8.3.1 Three Phase Smart Gate Drivers

The DRV835x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support. The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.

The DRV835x family of devices implement a smart gate-drive architecture which allows the user to dynamically adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this architecture provides a variety of protection features for the external MOSFETs including automatic dead-time insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.

8.3.1.1 PWM Control Modes

The DRV835x family of devices provides four different PWM control modes to support various commutation and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or PWM_MODE change.

8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)

In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The corresponding INHx and INLx signals control the output state as listed in Table 1.

Table 1. 6x PWM Mode Truth Table

8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)

In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 2.

Table 2. 3x PWM Mode Truth Table

8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)

In this mode, the DRV835x family of devices uses 6-step block commutation tables that are stored internally. This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the halfbridges.

The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.

The INHC input controls the direction through the 6-step commutation table which is used to change the direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin low if this feature is not required.

The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this feature is not required.

Table 3. Synchronous 1x PWM Mode

Table 4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)

Figure 22 and Figure 23 show the different possible configurations in 1x PWM mode.

Figure 22. 1x PWM—Simple Controller Figure 23. 1x PWM—Hall Sensor

8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)

In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835x or to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches. In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side and low-side MOSFETs are turned on at the same time.

Table 5. Independent PWM Mode Truth Table

Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the monitors is not possible if both the high-side and low-side gate drivers are being operated independently.

In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in Figure 24.

Figure 24. Independent PWM High-Side and Low-Side Drivers

If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is still possible. Connect the SHx pin as shown in Figure 25 or Figure 26. The unused gate driver and the corresponding input can be left disconnected.

Figure 25. Single High-Side Driver Figure 26. Single Low-Side Driver

8.3.1.2 Device Interface Modes

The DRV835x family of devices support two different interface modes (SPI and hardware) to allow the end application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different versions to be pin to pin compatible. This allows for application designers to evaluate with one interface version and potentially switch to another with minimal modifications to their design.

8.3.1.2.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that allows for an external controller to send and receive data with the DRV835x. This allows for the external controller to configure device settings and read detailed fault information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.

• The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on SDI and SDO.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup resistor.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the DRV835x.

For more information on the SPI, see the SPI Communication section.

8.3.1.2.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE, MODE, and VDS. This allows for the application designer to configure the most commonly used device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT pin.

• The GAIN pin configures the current shunt amplifier gain.
• The IDRIVE pin configures the gate drive current strength.
• The MODE pin configures the PWM control mode.
• The VDS pin configures the voltage threshold of the VDS overcurrent monitors.

For more information on the hardware interface, see the Pin Diagrams section.

Figure 27. SPI Figure 28. Hardware Interface

8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations

The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed output voltage of V_VDRAIN + 10.5 V and supports an average output current of 25 mA. When V_VM is less than 12 V, the charge pump operates in full doubler mode and generates V_VCP = 2 × V_VM - 1.5 V with respect to V_VDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions.

The charge pump requires a X5R or X7R, 1-μ F , 16-V ceramic capacitor between the VDRAIN and VCP pins to act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required between the CPH and CPL pins to act as the flying capacitor.

Figure 29. Charge Pump Architecture

The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a X5R or X7R, 1-μF, 16-V ceramic capacitor between VGLS and GND.

Since the charge pump output is regulated to V_VDRAIN + 10.5 V this allows for VM to be supplied either directly from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an externally available power supply. On the DRV8350R and DRV8353R devices the integrated buck regulator can be used to create the efficient low voltage supply for VM without the need for an additional regulator. Figure 30 and Figure 31 show examples of the DRV835x configured in either single supply or dual supply configuration.

Figure 31. Dual Supply Example

8.3.1.4 Smart Gate Drive Architecture

The DRV835x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and lowside drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.

Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive Control section. Figure 32 shows the high-level functional block diagram of the gate driver.

The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters of the external power MOSFET used in the system and the desired rise and fall times (see the Application and Implementation section).

The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from overvoltage conditions in the case of external short-circuit events on the MOSFET.

Figure 32. Gate Driver Block Diagram

8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control

The IDRIVE component implements adjustable gate-drive current to control the MOSFET V_DS slew rates. The MOSFET V_DS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics in the external half-bridge. IDRIVE operates on the principal that the MOSFET V_DS slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET Q_GD or Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external power MOSFETs.

IDRIVE allows the DRV835x family of devices to dynamically switch between gate drive currents either through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide 16 I_DRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices provides 7 I_DRIVE settings between the same ranges. The gate drive current setting is delivered to the gate during the turnon and turnoff of the external power MOSFET for the t_DRIVE duration. After the MOSFET turnon or turnoff, the gate driver switches to a smaller hold I_HOLD current to improve the gate driver efficiency. Additional details on the IDRIVE settings are described in the Register Maps section for the SPI devices and in the Pin Diagrams section for the hardware interface devices.

8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control

The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.

The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross conduct and cause shoot-through. The DRV835x family of devices use V_GS voltage monitors to measure the MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and variation in the MOSFET parameters. An additional digital dead time (t_DEAD) can be inserted and is adjustable through the registers on SPI devices.

The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the high-side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due to the need to discharge the voltage present on the internal V_{rm GS} detection circuit.

The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state machine enables a strong pulldown I_STRONG current on the opposite MOSFET gate whenever a MOSFET is switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.

The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair of V_GS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at the end of the t_DRIVE period the V_GS voltage has not reached the correct threshold the gate driver will report a fault. To make sure that a false fault is not detected, a t_DRIVE time should be selected that is longer than the time required to charge or discharge the MOSFET gate. The t_DRIVE time does not increase the PWM time and will terminate if another PWM command is received while active. Additional details on the TDRIVE settings are described in the Register Maps section for SPI devices and in the Pin Diagrams section for hardware interface devices.

Figure 33 shows an example of the TDRIVE state machine in operation.

Figure 33. TDRIVE State Machine

8.3.1.4.3 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to a detected output change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay, and the delay through the analog gate drivers.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall propagation delay of the device.

8.3.1.4.4 MOSFET V_DS Monitors

The gate drivers implement adjustable V_DS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the V_DS trip point (V_VDSOCP) for longer than the deglitch time (t_OCP) , an overcurrent condition is detected and action is taken according to the device V_DS fault mode.

The high-side V_DS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three current-shunt amplifiers (DRV8353 and DRV8353R), the low-side V_DS monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the external half-bridges. On device options without the current shunt amplifiers (DRV8350 and DRV8350R) the low-side V_DS monitor measures between the SHx and SLx pins.

For the SPI devices, the low-side V_DS monitor reference point can be changed between the SPx and SNx pins if desired with the LS_REF register setting. This is only for the low-side V_DS monitor. The high-side V_DS monitor stays between the VDRAIN and SHx pins.

The V_{VDS_OCP} threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on hardware interface devices. Additional information on the V_DS monitor levels are described in the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.

Figure 34. DRV8350 and DRV8350R V_DS Monitors

Figure 35. DRV8353 and DRV8353R V_DS Monitors

8.3.1.4.5 VDRAIN Sense and Reference Pin

The DRV835x family of devices provides a separate sense and reference pin for the common point of the high-side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors (VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.

The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge pump reference stays with respect to the power MOSFET supply through voltage transient conditions.

Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can be supplied from an efficient low voltage supply to increase the device efficiency. On the DRV8350R and DRV8353R devices, the integrated buck regulator can be used to create the efficient low voltage supply.

8.3.2 DVDD Linear Voltage Regulator

A 5-V, 10-mA linear regulator is integrated into the DRV835x family of devices and is available for use by external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-μF, 6.3-V ceramic capacitor routed directly back to the adjacent DGND or GND ground pin.

The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator functions like a constant-current source. The output voltage drops significantly with a current load greater than 10 mA.

Figure 36. DVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.

$P = (V_VM - V_DVDD) × I_DVDD$ (1)

For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.

$P = (24 V - 3.3 V) × 20 mA = 414 mW(2)

8.3.3 Pin Diagrams

Figure 37 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.

Figure 37. Logic-Level Input Pin Structure

Figure 38 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The input can be set with an external resistor.

Figure 38. Four Level Input Pin Structure

Figure 39 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices. The input can be set with an external resistor.

Figure 39. Seven Level Input Pin Structure

Figure 40 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires an external pullup resistor to function correctly.

Figure 40. Open-Drain Output Pin Structure

8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)

The DRV8353 and DRV8353R integrate three, high-performance low-side current-shunt amplifiers for current measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin (VREF).

8.3.4.1 Bidirectional Current Sense Operation

The SOx pin on the DRV8353 and DRV8353R outputs an analog voltage equal to the voltage across the SPx and SNx pins multiplied by the gain setting (G_{CSA}$ ). The gain setting is adjustable between four different levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.

$I = frac{frac{V_VREF}{2} - V_SOx}{G_CSA × R_SENSE}(3)

Figure 41. Bidirectional Current-Sense Configuration

Figure 42. Bidirectional Current-Sense Output

Figure 43. Bidirectional Current Sense Regions

8.3.4.2 Unidirectional Current Sense Operation (SPI only)

On the DRV8353 and DRV8353R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case the shunt amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across the SPx and SNx pins multiplied by the gain setting (G_{CSA}$ ). Use Equation 4 to calculate the current through the shunt resistor.

$I = frac{V_VREF - V_SOx}{G_CSA × R_SENSE}(4)

Figure 44. Unidirectional Current-Sense Configuration

Figure 45. Unidirectional Current-Sense Output

Figure 46. Unidirectional Current-Sense Regions

8.3.4.3 Amplifier Calibration Modes

To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during the switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration mode is shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration mode.

Figure 47. Amplifier Manual Calibration

In addition to the manual calibration method provided on the SPI devices versions, the DRV835x family of devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize the amplifier input offset after power up and during run time to account for temperature and device variation.

Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage. 50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to minimize the amplifier input offset. After this the amplifiers are ready for normal operation.

For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain setting in order to improve the accuracy of the calibration routine.

at T^A = –40°C to +125°C (unless otherwise noted)(1)

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

⁽²⁾ VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum. This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

7.2 ESD Ratings

⁽¹⁾ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.

at T^A = –40°C to +125°C (unless otherwise noted)

⁽¹⁾ Power dissipation and thermal limits must be observed.

The DRV835x family of devices are primarily used in three-phase brushless DC motor control applications. The design procedures in the Typical Application section highlight how to use and configure the DRV835x family of devices.

9.2 Typical Application

9.2.1 Primary Application

The DRV8353R is shown being used for a single supply, three-phase BLDC motor drive with individual halfbridge current sense in this application example.