DAC8562SDSCR

Part: Texas Instruments DAC7562, DAC7563, DAC8162, DAC8163, DAC8562, DAC8563

Type: Dual 16-, 14-, 12-Bit, Low-Power, Buffered, Voltage-Output Digital-to-Analog Converters With 2.5-V, 4-PPM/°C Internal Reference

Key Specs:

• Relative Accuracy (INL) DAC756x (12-Bit): 0.3 LSB
• Relative Accuracy (INL) DAC816x (14-Bit): 1 LSB
• Relative Accuracy (INL) DAC856x (16-Bit): 4 LSB
• Glitch Impulse: 0.1 nV-s
• Internal Reference Voltage: 2.5 V
• Internal Reference Initial Accuracy: ±5 mV (Max)
• Internal Reference Temperature Drift: 4 ppm/°C (Typ)
• Internal Reference Sink and Source Capability: 20 mA
• Low-Power Consumption: 4 mW (Typ, 5-V AVDD, Including Internal Reference Current)
• Power-Supply Range: 2.7 V to 5.5 V
• SPI Clock Rate: 50 MHz
• Temperature Range: –40°C to 125°C

Features:

• Low-power, voltage-output, dual-channel
• 16-, 14-, and 12-bit resolution options
• Includes a 2.5-V, 4-ppm/°C internal reference
• Monotonicity, excellent linearity, and minimized code-to-code transient voltages
• Three-wire serial interface (up to 50 MHz) compatible with SPI, QSPI, Microwire, and DSP interfaces
• Power-on-reset circuit to zero scale (DACxx62) or mid-scale (DACxx63)
• Power-down feature (reduces current consumption to 550 nA at 5 V)
• LDAC and CLR functions
• Output buffer with rail-to-rail operation
• Bidirectional Reference: Input or 2.5-V Output
• Schmitt-Triggered Inputs for SPI

Applications:

• Portable Instrumentation
• PLC Analog Output Module
• Voltage Controlled Oscillator Tuning
• Programmable Gain and Offset Adjustment
• Portable, battery-operated equipment

Package:

• WSON-10: 3.00 mm x 3.00 mm (body size)
• VSSOP-10: 3.00 mm x 3.00 mm (body size)
• SON-10

Tools & Software

¹ The DAC756x, DAC816x, and DAC856x devices are • Relative Accuracy: low-power, voltage-output, dual-channel, 16-, 14-, – DAC756x (12-Bit): 0.3 LSB INL and 12-bit digital-to-analog converters (DACs), – DAC816x (14-Bit): 1 LSB INL respectively. These devices include a 2.5-V, – DAC856x 4-ppm/°C internal reference, giving a full-scale output (16-Bit): 4 LSB INL voltage range of 2.5 V or 5 V. The internal reference • Glitch Impulse: 0.1 nV-s has an initial accuracy of ±5 mV and can source or • Bidirectional Reference: Input or 2.5-V Output sink up to 20 mA at the VREFIN/VREFOUT pin.

– Output Disabled by Default These devices are monotonic, providing excellent – ±5-mV Initial Accuracy (Max) linearity and minimizing undesired code-to-code – 4-ppm°C Temperature Drift transient voltages (glitch). They use a versatile three- (Typ) wire serial interface that operates at clock rates up to – 10-ppm/°C Temperature Drift (Max) ⁵⁰ MHz. The interface is compatible with standard – 20-mA Sink and Source Capability SPI™, QSPI™, Microwire, and digital signal • Power-On Reset to Zero Scale or Mid-Scale processor (DSP) interfaces. The DACxx62 devices incorporate ^a power-on-reset circuit that ensures the • Low-Power: ⁴ mW (Typ, 5-V AVDD, Including DAC output powers up and remains at zero scale Internal Reference Current) until ^a valid code is written to the device, whereas the • Wide Power-Supply Range: 2.7 V to 5.5 V DACxx63 devices similarly power up at mid-scale. • 50-MHz SPI With Schmitt-Triggered Inputs These devices contain a power-down feature that reduces current consumption to typically 550 nA at • LDAC and CLR Functions 5 V. The low power consumption, internal reference, • Output Buffer With Rail-to-Rail Operation and small footprint make these devices ideal for

• Temperature Range: –40°C to 125°C The DACxx62 devices are drop-in and functioncompatible with each other, as are the DACxx63 2 Applications devices. The entire family is available in MSOP-10

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DAC8562	VSSOP (10), WSON (10)	3.00 mm x 3.00 mm
DAC8162	VSSOP (10), WSON (10)	3.00 mm x 3.00 mm
DAC7562	VSSOP (10), WSON (10)	3.00 mm x 3.00 mm

Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

1

SLAS719E –AUGUST 2010–REVISED JUNE 2015 www.ti.com

When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the RSET resistor from the SET pin to VREF to apply the offset and obtain the transfer function shown in Equation 6.

$mathbf{M}_mathbf{OUT} = mathbf{10} × ≤ft(frac{mathbf{V_DAC} - mathbf{V_REF}}{mathbf{R_SEF}}right) tag{6}$

The desired output ranges for VDAC and VREF voltages determine the RSET and R^G resistor values, calculated using Equation 7 and Equation 8. The system design requires a VDAC voltage range of 0.04 V to 4.96 V in order to operate the DAC8563 in the specified linear output range from codes 512 to 65 024.

$mathsf{R_SET} &= mathsf{10} × ≤ft(frac{mathsf{V_DAC} - mathsf{V_REF}}{mathsf{I_OUT}}right) = mathsf{10} × ≤ft(frac{mathsf{4.96 mathsf{V} - 2.5 mathsf{V}}}{mathsf{0.024 mathsf{A}}}right) = mathsf{1025 mathsf{O}} mathsf{R_G} &= frac{mathsf{2 × mathsf{V_OUT}mathsf{MAX} × mathsf{R_SET}}{mathsf{V_DAC} - mathsf{V_REF}} = frac{mathsf{2 × mathsf{10} mathsf{V} × mathsf{1020} mathsf{O}}{mathsf{4.96 mathsf{V} - 2.5 mathsf{V}}} = mathsf{8292 mathsf{O}} tag{7}$

IMON and IAOUT accomplish load monitoring. The sizing of RIMON and RIA determine the monitoring output voltage across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load current IDRV.

$mathsf{PR}_mathsf{MOON} &= frac{mathsf{TO} × mathsf{V}_mathsf{MOON}}{mathsf{l}_mathsf{DFSV}} mathsf{PR}_mathsf{M} &= frac{mathsf{TO} × mathsf{V}_mathsf{M}}{mathsf{l}_mathsf{M}} tag{9}For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).

Typical Applications (continued)

9.2.1.3 Application Curves

Figure 97 shows the transfer function for the bipolar ±10 V voltage range. This design also supports output voltage ranges of 0–5 V, 0–10 V and ±5 V. Figure 98 shows the transfer function for the unipolar 0–24 mA current range. This design also supports output current ranges of ±24 mA and 4 mA–20 mA.

SLAS719E –AUGUST 2010–REVISED JUNE 2015 www.ti.com

Typical Applications (continued)

9.2.2 Up to ±15-V Bipolar Output Using the DAC8562

The DAC8562 is designed to be operate from a single power supply providing a maximum output range of AVDD volts. However, the DAC can be placed in the configuration shown in Figure 99 in order to be designed into bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from ±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference enabled and the DAC8562 internal gain set to 2, however, an external 2.5-V reference could also be used (with DAC8562 internal gain set to 2).

Figure 99. Bipolar Output Range Circuit Using DAC8562

The transfer function shown in Equation 5 can be used to calculate the output voltage as a function of the DAC code, reference voltage and resistor ratio:mathbb{V}_{rm OUT} = mathbb{G} × mathbb{V}_{rm RECOUT} ≤ft( 2 × frac{mathbb{D}_{rm IN}}{65,536} - 1 right) tag{11}$

where:

DIN = decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for DAC8562 (16 bit).

VREFOUT = reference output voltage with the internal reference enabled from the DAC VREFIN/VREFOUT pin G = ratio of the resistors

An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and VREFOUT = 2.5 V:

$V_OUT = 20 × frac{D_IN}{65,536} - textdegree 10 V tag{12}$

In this example, the range is set to ±10 V by using a resistor ratio of four, VREFOUT of 2.5 V, and DAC8562 internal gain of 2. The resistor sizes must be selected keeping in mind the current sink or source capability of the DAC8562 internal reference. Using larger resistor values, for example, R = 10 kΩ or larger, is recommended. The op amp is selectable depending on the requirements of the system.

The DAC8562EVM and DAC7562EVM boards have the option to evaluate the bipolar output application by installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or DAC7562EVM product folder.

9.3 System Examples

9.3.1 MSP430 Microprocessor Interfacing

Figure 100 shows a serial interface between the DAC756x, DAC816x, or DAC856x device and a typical MSP430 USI port such as the one found on the MSP430F2013. The port is configured in SPI master mode by setting bits 3, 5, 6, and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means of SPI communication with minimal software overhead. The serial clock polarity, source, and speed are controlled by settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-programmable pin on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the DAC756x, DAC816x, or DAC856x device, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P1.4 is taken high following the completion of the third write cycle.

NOTE: Additional pins omitted for clarity.

9.3.2 TMS320 McBSP Microprocessor Interfacing

Figure 101 shows an interface between the DAC756x, DAC816x, or DAC856x device and any TMS320 series DSP from Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out on the rising edge of the serial clock and are clocked into the DAC756x, DAC816x, or DAC856x device on the falling edge of the SCLK signal.

Figure 101. DAC756x, DAC816x, or DAC856x Device to TMS320 McBSP Interface

9.3.3 OMAP-L1x Processor Interfacing

Figure 102 shows a serial interface between the DAC756x, DAC816x, or DAC856x device and the OMAP-L138 processor. The transmit clock CLKx0 of the L138 drives SCLK of the DAC756x, DAC816x, or DAC856x device, and the data transmit (Dx0) output drives the serial data line of the DAC. The SYNC signal is derived from the frame sync transmit (FSx0) line, similar to the TMS320 interface.

NOTE: Additional pins omitted for clarity.

Figure 102. DAC756x, DAC816x, or DAC856x Device to OMAP-L1x Processor

(1) TI recommends connecting the thermal pad to the ground plane for better thermal dissipation.

Pin Functions

• NAME
• AVDD
• CLR
• DIN
• GND
• LDAC
• SCLK
• SYNC
• VOUTA
• VOUTB
• VREFIN/VREFOUT

At AVDD = 2.7 V to 5.5 V and T^A = –40°C to 125°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC PERFORMANCE(1)
DAC856x	Resolution		16			Bits
	Relative accuracy	Using line passing through codes 512 and 65,024		±4	±12	LSB
	Differential nonlinearity	16-bit monotonic		±0.2	±1	LSB
DAC816x	Resolution		14			Bits
	Relative accuracy	Using line passing through codes 128 and 16,256		±1	±3	LSB
	Differential nonlinearity Resolution	14-bit monotonic	12	±0.1	±0.5	LSB Bits
DAC756x	Relative accuracy	Using line passing through codes 32 and 4,064		±0.3	±0.75	LSB
	Differential nonlinearity	12-bit monotonic		±0.05	±0.25	LSB
Offset error		Extrapolated from two-point line(1) , unloaded		±1	±4	mV
Offset error drift				±2		μV/°C
Full-scale error		DAC register loaded with all 1s		±0.03	±0.2	% FSR
Zero-code error		DAC register loaded with all 0s		1	4	mV
Zero-code error drift				±2		μV/°C
Gain error		Extrapolated from two-point line(1) , unloaded		±0.01	±0.15	% FSR
Gain temperature coefficient	OUTPUT CHARACTERISTICS(2)			±1		ppm FSR/°C
Output voltage range			0		AVDD	V
	Output voltage settling time(3)	DACs unloaded RL = 1 MΩ		7 10		μs
Slew rate		Measured between 20%–80% of a full-scale transition RL = ∞		0.75 1		V/μs nF
Capacitive load stability		RL = 2 kΩ		3
Code-change glitch impulse		1-LSB change around major carry		0.1		nV-s
Digital feedthrough		SCLK toggling, SYNC high		0.1		nV-s
Power-on glitch impulse		RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V		40		mV
Channel-to-channel dc crosstalk		Full-scale swing on adjacent channel, External reference Full-scale swing on adjacent channel, Internal reference		5 15		μV
DC output impedance		At mid-scale input		5		Ω
Short-circuit current		DAC outputs at full-scale, DAC outputs shorted to GND		40		mA
Power-up time, including settling time		Coming out of power-down mode		50		μs
AC PERFORMANCE(2)
DAC output noise density		TA = 25°C, at mid-scale input, fOUT = 1 kHz		90		nV/√Hz
DAC output noise		TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz		2.6		μVPP

(2) Specification based on design or characterization. Not production tested

(3) Transition time between 1 / 4 scale and 3 / 4 scale, including settling to within ±0.024% FSR

Over operating ambient temperature range (unless otherwise noted).

	MIN	MAX	UNIT
AVDD to GND	–0.3	6	V
CLR, DIN, LDAC, SCLK and SYNC input voltage to GND	–0.3	AVDD + 0.3	V
VOUT[A, B] to GND	–0.3	AVDD + 0.3	V
VREFIN/VREFOUT to GND	–0.3	AVDD + 0.3	V
Operating temperature range	–40	125	°C
Junction temperature, TJ		150	°C
Storage temperature, Tstg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

over operating ambient temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
POWER SUPPLY
	Supply voltage	2.7		5.5	V
DIGITAL INPUTS
	Digital input voltage	0		AVDD	V
REFERENCE INPUT
VREFIN	Reference input voltage	0		AVDD	V
TEMPERATURE RANGE
TA	Operating ambient temperature	-40		125	°C

7.4 Thermal Information

		DAC756x, DAC816x, DAC856x
	THERMAL METRIC	DSC (WSON)	DGS (VSSOP)	UNIT
		10 PINS	10 PINS
RθJA	Junction-to-ambient thermal resistance	62.8	173.8	°C/W
RθJC(top)	Junction-to-case (top) thermal resistance	44.3	48.5	°C/W
RθJB	Junction-to-board thermal resistance	26.5	79.9	°C/W
ψJT	Junction-to-top characterization parameter	0.4	1.7	°C/W
ψJB	Junction-to-board characterization parameter	25.5	68.4	°C/W
RθJC(bot)	Junction-to-case (bottom) thermal resistance	46.2	N/A	°C/W

7.5 Electrical Characteristics

At AVDD = 2.7 V to 5.5 V and T^A = –40°C to 125°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC PERFORMANCE(1)
DAC856x	Resolution		16			Bits
	Relative accuracy	Using line passing through codes 512 and 65,024		±4	±12	LSB
	Differential nonlinearity	16-bit monotonic		±0.2	±1	LSB
DAC816x	Resolution		14			Bits
	Relative accuracy	Using line passing through codes 128 and 16,256		±1	±3	LSB
	Differential nonlinearity Resolution	14-bit monotonic	12	±0.1	±0.5	LSB Bits
DAC756x	Relative accuracy	Using line passing through codes 32 and 4,064		±0.3	±0.75	LSB
	Differential nonlinearity	12-bit monotonic		±0.05	±0.25	LSB
Offset error		Extrapolated from two-point line(1) , unloaded		±1	±4	mV
Offset error drift				±2		μV/°C
Full-scale error		DAC register loaded with all 1s		±0.03	±0.2	% FSR
Zero-code error		DAC register loaded with all 0s		1	4	mV
Zero-code error drift				±2		μV/°C
Gain error		Extrapolated from two-point line(1) , unloaded		±0.01	±0.15	% FSR
Gain temperature coefficient	OUTPUT CHARACTERISTICS(2)			±1		ppm FSR/°C
Output voltage range			0		AVDD	V
	Output voltage settling time(3)	DACs unloaded RL = 1 MΩ		7 10		μs
Slew rate		Measured between 20%–80% of a full-scale transition RL = ∞		0.75 1		V/μs nF
Capacitive load stability		RL = 2 kΩ		3
Code-change glitch impulse		1-LSB change around major carry		0.1		nV-s
Digital feedthrough		SCLK toggling, SYNC high		0.1		nV-s
Power-on glitch impulse		RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V		40		mV
Channel-to-channel dc crosstalk		Full-scale swing on adjacent channel, External reference Full-scale swing on adjacent channel, Internal reference		5 15		μV
DC output impedance		At mid-scale input		5		Ω
Short-circuit current		DAC outputs at full-scale, DAC outputs shorted to GND		40		mA
Power-up time, including settling time		Coming out of power-down mode		50		μs
AC PERFORMANCE(2)
DAC output noise density		TA = 25°C, at mid-scale input, fOUT = 1 kHz		90		nV/√Hz
DAC output noise		TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz		2.6		μVPP

(2) Specification based on design or characterization. Not production tested

(3) Transition time between 1 / 4 scale and 3 / 4 scale, including settling to within ±0.024% FSR

Electrical Characteristics (continued)

At AVDD = 2.7 V to 5.5 V and T^A = –40°C to 125°C (unless otherwise noted).

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC PERFORMANCE(1)
DAC856x
Resolution				16	Bits
Relative accuracy	Using line passing through codes 512 and 65,024		±4	±12	LSB
Differential nonlinearity	16-bit monotonic		±0.2	±1	LSB
DAC816x
Resolution				14	Bits
Relative accuracy	Using line passing through codes 128 and 16,256		±3	±8	LSB
Differential nonlinearity	14-bit monotonic		±0.1	±0.5	LSB
DAC756x
Resolution				12	Bits
Relative accuracy	Using line passing through codes 32 and 4,064		±0.3	±0.75	LSB
Differential nonlinearity	12-bit monotonic		±0.05	±0.25	LSB
Offset error	Extrapolated from two-point line(1), unloaded		±1	±4	mV
Offset error drift			±2		µV/°C
Full-scale error	DAC register loaded with all 1s		±0.03	±0.2	% FSR
Zero-code error	DAC register loaded with all 0s		1	4	mV
Zero-code error drift			±2		µV/°C
Gain error	Extrapolated from two-point line(1), unloaded		±0.01	±0.15	% FSR
Gain temperature coefficient			±1		ppm FSR/°C
OUTPUT CHARACTERISTICS(2)
Output voltage range	DACs unloaded	0		AVDD	V
Output voltage settling time(3)	RL = 1 MΩ		7	10	µs
Slew rate	Measured between 20%–80% of a full-scale transition		0.75		V/µs
Capacitive load stability	RL = ∞		1		nF
	RL = 2 kΩ		3		nF
Code-change glitch impulse	1-LSB change around major carry		0.1		nV-s
Digital feedthrough	SCLK toggling, SYNC high		0.1		nV-s
Power-on glitch impulse	RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V		40		mV
Channel-to-channel dc crosstalk	Full-scale swing on adjacent channel, External reference		5		µV
	Full-scale swing on adjacent channel, Internal reference		15		µV
DC output impedance	At mid-scale input		5		Ω
Short-circuit current	DAC outputs at full-scale, DAC outputs shorted to GND		40		mA
Power-up time, including settling time	Coming out of power-down mode		50		µs
AC PERFORMANCE(2)
DAC output noise density	TA = 25°C, at mid-scale input, fOUT = 1 kHz		90		nV/√Hz
DAC output noise	TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz		2.6		µVPP

Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DAC7562 DAC7563 DAC8162 DAC8163 DAC8562 DAC8563

SLAS719E –AUGUST 2010–REVISED JUNE 2015 www.ti.com

Electrical Characteristics (continued)

At AVDD = 2.7 V to 5.5 V and T^A = –40°C to 125°C (unless otherwise noted).

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER REQUIREMENTS(5)
	AVDD = 3.6 V to 5.5 V, normal mode, internal reference off		0.25	0.5	mA
	AVDD = 3.6 V to 5.5 V, normal mode, internal reference on		0.9	1.6	mA
	AVDD = 3.6 V to 5.5 V, power-down modes(6)
(5) Input code = mid-scale, no load, VINH = AVDD, and VINL = GND

(6) T^A = –40°C to 105°C

7.6 Timing Requirements(1)(2)

At AVDD = 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted).

		DAC756x, DAC816x, DAC856x		UNIT
		MIN	TYP	MAX
f(SCLK)	Serial clock frequency			50
t(1)	SCLK falling edge to SYNC falling edge (for successful write operation)	10
t(2)	SCLK cycle time	20
t(3)	SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt)	13
t(4)	Minimum SYNC HIGH time	80
t(5)	SYNC to SCLK falling edge setup time	13
t(6)	SCLK LOW time	8
t(7)	SCLK HIGH time	8
t(8)	SCLK falling edge to SYNC rising edge	10
t(9)	Data setup time	6
t(10)	Data hold time	5
t(11)	SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode	5
t(12)	LDAC pulse duration, LOW time	10
t(13)	CLR pulse duration, LOW time	80
t(14)	CLR falling edge to start of VOUT transition			100

(1) All input signals are specified with t^r = t^f = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2.

(2) See the Serial Write Operation timing diagram (Figure 1).

(1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.

(2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Serial Write Operation

SLAS719E –AUGUST 2010–REVISED JUNE 2015 www.ti.com

7.7 Typical Characteristics

Table 1. Typical Characteristics: Internal Reference Performance

MEASUREMENT	POWER-SUPPLY VOLTAGE	FIGURE NUMBER
Internal Reference Voltage vs Temperature		Figure 2
Internal Reference Voltage Temperature Drift Histogram		Figure 3
Internal Reference Voltage vs Load Current	5.5 V	Figure 4
Internal Reference Voltage vs Time		Figure 5
Internal Reference Noise Density vs Frequency		Figure 6
Internal Reference Voltage vs Supply Voltage	2.7 V–5.5 V	Figure 7

Table 2. Typical Characteristics: DAC Static Performance

MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS
Full-Scale Error vs Temperature		Figure 16
Gain Error vs Temperature		Figure 17
Offset Error vs Temperature		5.5 V	Figure 18
Zero-Code Error vs Temperature			Figure 19
Full-Scale Error vs Temperature			Figure 63
Gain Error vs Temperature			Figure 64
Offset Error vs Temperature		2.7 V	Figure 65
Zero-Code Error vs Temperature		Figure 66
LOAD REGULATION
		5.5 V	Figure 30
DAC Output Voltage vs Load Current		2.7 V	Figure 74
DIFFERENTIAL NONLINEARITY ERROR
	T = –40°C		Figure 9
Differential Linearity Error vs Digital Input Code	T = 25°C	5.5 V	Figure 11
	T = 125°C		Figure 13
Differential Linearity Error vs Temperature		Figure 15
	T = –40°C		Figure 56
Differential Linearity Error vs Digital Input Code	T = 25°C		Figure 58
	T = 125°C	2.7 V	Figure 60
Differential Linearity Error vs Temperature			Figure 62
INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)
	T = –40°C		Figure 8
Linearity Error vs Digital Input Code	T = 25°C	5.5 V	Figure 10
	T = 125°C		Figure 12
Linearity Error vs Temperature			Figure 14
	T = –40°C		Figure 55
Linearity Error vs Digital Input Code	T = 25°C		Figure 57
	T = 125°C	2.7 V	Figure 59
Linearity Error vs Temperature			Figure 61

MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
POWER-DOWN CURRENT
Power-Down Current vs Temperature		5.5 V	Figure 28
Power-Down Current vs Power-Supply Voltage		2.7 V – 5.5 V	Figure 29
Power-Down Current vs Temperature		2.7 V	Figure 73
POWER-SUPPLY CURRENT
Power-Supply Current vs Temperature	External VREF		Figure 20
	Internal VREF		Figure 21
	External VREF		Figure 22
Power-Supply Current vs Digital Input Code	Internal VREF	5.5 V	Figure 23
Power-Supply Current Histogram	External VREF		Figure 24
	Internal VREF		Figure 25
	External VREF	2.7 V – 5.5 V	Figure 26
Power-Supply Current vs Power-Supply Voltage	Internal VREF		Figure 27
Power-Supply Current vs Temperature	External VREF	3.6 V	Figure 49
	Internal VREF		Figure 50
	External VREF		Figure 51
Power-Supply Current vs Digital Input Code	Internal VREF		Figure 52
	External VREF		Figure 53
Power-Supply Current Histogram	Internal VREF		Figure 54
Power-Supply Current vs Temperature	External VREF		Figure 67
	Internal VREF		Figure 68
Power-Supply Current vs Digital Input Code	External VREF		Figure 69
	Internal VREF	2.7 V	Figure 70
	External VREF		Figure 71
Power-Supply Current Histogram	Internal VREF		Figure 72

Table 2. Typical Characteristics: DAC Static Performance (continued)

Table 3. Typical Characteristics: DAC Dynamic Performance

MEASUREMENT	POWER-SUPPLY VOLTAGE	FIGURE NUMBER
Table 1. Typical Characteristics: Internal Reference Performance
Internal Reference Voltage vs Temperature		Figure 2
Internal Reference Voltage Temperature Drift Histogram		Figure 3
Internal Reference Voltage vs Load Current	5.5 V	Figure 4
Internal Reference Voltage vs Time		Figure 5
Internal Reference Noise Density vs Frequency		Figure 6
Internal Reference Voltage vs Supply Voltage	2.7 V–5.5 V	Figure 7
Table 2. Typical Characteristics: DAC Static Performance
**FULL-SCALE, GAIN,

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MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
	Rising Edge, Code 7FFFh to 8000h		Figure 79
Glitch Impulse, 1-LSB Step	Falling Edge, Code 8000h to 7FFFh		Figure 80
	Rising Edge, Code 7FFCh to 8000h		Figure 81
Glitch Impulse, 4-LSB Step	Falling Edge, Code 8000h to 7FFCh	2.7 V	Figure 82
	Rising Edge, Code 7FF0h to 8000h		Figure 83
Glitch Impulse, 16-LSB Step	Falling Edge, Code 8000h to 7FF0h		Figure 84
NOISE
DAC Output Noise Density vs	External VREF		Figure 45
Frequency	Internal VREF	5.5 V	Figure 46
DAC Output Noise 0.1 Hz to 10 Hz	External VREF		Figure 47
POWER-ON GLITCH
	Reset to Zero Scale		Figure 35
	Reset to Midscale	5.5 V	Figure 36
Power-On Glitch	Reset to Zero Scale		Figure 85
	Reset to Midscale	2.7 V	Figure 86
SETTLING TIME
Full-Scale Settling Time	Rising Edge, Code 0h to FFFFh		Figure 31
	Falling Edge, Code FFFFh to 0h		Figure 32
Half-Scale Settling Time	Rising Edge, Code 4000h to C000h	5.5 V	Figure 33
	Falling Edge, Code C000h to 4000h		Figure 34
Full-Scale Settling Time	Rising Edge, Code 0h to FFFFh		Figure 75
	Falling Edge, Code FFFFh to 0h		Figure 76
	Rising Edge, Code 4000h to C000h	2.7 V	Figure 77
Half-Scale Settling Time	Falling Edge, Code C000h to 4000h		Figure 78

Table 3. Typical Characteristics: DAC Dynamic Performance (continued)

7.7.1 Typical Characteristics: Internal Reference

At T^A = 25°C, AVDD = 5.5 V, gain = 2, and VREFOUT unloaded, unless otherwise noted.

DAC7562, DAC7563, DAC8162 DAC8163, DAC8562, DAC8563

SLAS719E –AUGUST 2010–REVISED JUNE 2015 www.ti.com

		DAC756x, DAC816x, DAC856x
	THERMAL METRIC	DSC (WSON)	DGS (VSSOP)	UNIT
		10 PINS	10 PINS
RθJA	Junction-to-ambient thermal resistance	62.8	173.8	°C/W
RθJC(top)	Junction-to-case (top) thermal resistance	44.3	48.5	°C/W
RθJB	Junction-to-board thermal resistance	26.5	79.9	°C/W
ψJT	Junction-to-top characterization parameter	0.4	1.7	°C/W
ψJB	Junction-to-board characterization parameter	25.5	68.4	°C/W
RθJC(bot)	Junction-to-case (bottom) thermal resistance	46.2	N/A	°C/W