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DAC8562SDGSR

Digital-to-Analog Converter (DAC)

The DAC8562SDGSR is a digital-to-analog converter (dac) from Analog Devices. View the full DAC8562SDGSR datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Analog Devices

Category

ADC / DAC

Overview

Part: DAC7562, DAC7563, DAC8162, DAC8163, DAC8562, DAC8563 — Texas Instruments

Type: Dual Voltage-Output Digital-to-Analog Converter (DAC)

Description: Low-power, dual-channel, 16-, 14-, and 12-bit digital-to-analog converters with a 2.5-V, 4-ppm/°C internal reference, 2.7 V to 5.5 V supply range, and 50-MHz SPI interface.

Operating Conditions:

  • Supply voltage: 2.7 V to 5.5 V
  • Operating temperature: -40°C to 125°C
  • SPI clock rate: up to 50 MHz

Absolute Maximum Ratings:

Key Specs:

  • Relative Accuracy (DAC756x): 0.3 LSB INL
  • Relative Accuracy (DAC816x): 1 LSB INL
  • Relative Accuracy (DAC856x): 4 LSB INL
  • Glitch Impulse: 0.1 nV-s
  • Internal Reference Initial Accuracy: ±5 mV (Max)
  • Internal Reference Temperature Drift: 4 ppm/°C (Typ), 10 ppm/°C (Max)
  • Internal Reference Sink/Source Capability: 20 mA
  • Power Consumption: 4 mW (Typ, 5-V AVDD, including internal reference current)
  • Power-down Current: 550 nA (Typ, 5 V)

Features:

  • Bidirectional Reference: Input or 2.5-V Output
  • Power-On Reset to Zero Scale or Mid-Scale
  • 50-MHz SPI With Schmitt-Triggered Inputs
  • LDAC and CLR Functions
  • Output Buffer With Rail-to-Rail Operation

Applications:

  • Portable Instrumentation
  • PLC Analog Output Module
  • Closed-Loop Servo Control
  • Voltage Controlled Oscillator Tuning
  • Data Acquisition Systems
  • Programmable Gain and Offset Adjustment

Package:

  • WSON-10 (3 mm × 3 mm)
  • VSSOP-10

Features

  • 1 · Relative Accuracy:
  • -DAC756x (12-Bit): 0.3 LSB INL
  • -DAC816x (14-Bit): 1 LSB INL
  • -DAC856x (16-Bit): 4 LSB INL
  • Glitch Impulse: 0.1 nV-s
  • Bidirectional Reference: Input or 2.5-V Output
  • -Output Disabled by Default
  • -±5-mV Initial Accuracy (Max)
  • -4-ppm°C Temperature Drift (Typ)
  • -10-ppm/°C Temperature Drift (Max)
  • -20-mA Sink and Source Capability
  • Power-On Reset to Zero Scale or Mid-Scale
  • Low-Power: 4 mW (Typ, 5-V AVDD, Including Internal Reference Current)
  • Wide Power-Supply Range: 2.7 V to 5.5 V
  • 50-MHz SPI With Schmitt-Triggered Inputs
  • LDAC and CLR Functions
  • Output Buffer With Rail-to-Rail Operation
  • Packages: WSON-10 (3 mm × 3 mm), VSSOP-10
  • Temperature Range: -40°C to 125°C

Applications

  • Portable Instrumentation
  • PLC Analog Output Module
  • Closed-Loop Servo Control
  • Voltage Controlled Oscillator Tuning
  • Data Acquisition Systems
  • Programmable Gain and Offset Adjustment

Pin Configuration

  • (1) TI recommends connecting the thermal pad to the ground plane for better thermal dissipation.

Electrical Characteristics

At AVDD = 2.7 V to 5.5 V and TA = -40°C to 125°C (unless otherwise noted).

PARAMETERPARAMETERTEST CONDITIONSMINTYPMAXUNIT
STATIC PERFORMANCE (1)STATIC PERFORMANCE (1)
Resolution
STATIC PERFORMANCE (1)STATIC PERFORMANCE (1)
16
STATIC PERFORMANCE (1)STATIC PERFORMANCE (1)STATIC PERFORMANCE (1)
Bits
Relative accuracyUsing line passing through codes 512 and 65,024±4±12LSB
Differential nonlinearity
Resolution
16-bit monotonic14±0.2±1LSB
Bits
Relative accuracyUsing line passing through codes 128 and 16,256±1±3LSB
Differential nonlinearity
Resolution
14-bit monotonic12±0.1±0.5LSB
Bits
Relative accuracyUsing line passing through codes 32 and 4,064±0.3±0.75LSB
Differential nonlinearity12-bit monotonic±0.05±0.25LSB
Offset errorOffset errorExtrapolated from two-point line (1) , unloaded±1±4mV
Offset error driftOffset error drift±2μV/°C
Full-scale errorFull-scale errorDAC register loaded with all 1s±0.03±0.2% FSR
Zero-code errorZero-code errorDAC register loaded with all 0s14mV
Zero-code error driftZero-code error drift±2μV/°C
Gain errorGain errorExtrapolated from two-point line (1) , unloaded±0.01±0.15% FSR
Gain temperature coefficientGain temperature coefficient±1ppm FSR/°C
OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)OUTPUT CHARACTERISTICS (2)
Output voltage rangeOutput voltage range0AV DDV
(3)DACs unloaded7μs
Output voltage settling timeOutput voltage settling timeR L = 1 M Ω10
Slew rateSlew rateMeasured between 20%-80% of a full-scale transition
R L = ∞
0.75
1
V/μs
nF
Capacitive load stabilityCapacitive load stabilityR L = 2 k Ω3
Code-change glitch impulseCode-change glitch impulse1-LSB change around major carry0.1 0.1nV-s
Digital feedthroughDigital feedthroughSCLK toggling, SYNC highnV-s
Power-on glitch impulsePower-on glitch impulseR L = 2 k Ω , C L = 470 pF, AV DD = 5.5 V40mV
Channel-to-channel dc crosstalkChannel-to-channel dc crosstalkFull-scale swing on adjacent channel, External reference5μV
DC output impedanceDC output impedanceFull-scale swing on adjacent channel, Internal reference
At mid-scale input DAC outputs at full-scale, DAC outputs shorted to
15 5Ω
mA
Short-circuit currentShort-circuit currentGND40
Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)Power-up time, including settling time Coming out of power-down mode 50 μs AC PERFORMANCE (2)
DAC output noise densityDAC output noise densityT A = 25°C, at mid-scale input, f OUT = 1 kHz90nV/ √ Hz
DAC output noiseDAC output noiseT A = 25°C, at mid-scale input, 0.1 Hz to 10 Hz2.6μV PP

Absolute Maximum Ratings

Over operating ambient temperature range (unless otherwise noted).

MINMAXUNIT
AV DD to GND-0.36V
CLR, D IN , LDAC, SCLK and SYNC input voltage to GND-0.3AV DD + 0.3V
V OUT [A, B] to GND-0.3AV DD + 0.3V
V REFIN /V REFOUT to GND-0.3AV DD + 0.3V
Operating temperature range-40125°C
Junction temperature, T J150°C
Storage temperature, T stg-65150°C

Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MINNOMMAXUNIT
POWER SUPPLY
Supply voltageAV DD to GND2.75.5V
DIGITAL INPUTS
Digital input voltageCLR, D IN , LDAC, SCLK and SYNC0AV DDV
REFERENCE INPUT
V REFINReference input voltage0AV DDV
TEMPERATURE RANGE
T AOperating ambient temperature-40125°C

Thermal Information

DAC756x, DAC816x, DAC856xDAC756x, DAC816x, DAC856x
THERMALMETRICDSC (WSON)DGS (VSSOP)
10 PINS10 PINS
R θ JAJunction-to-ambient thermal resistance62.8173.8
R θ JC(top)Junction-to-case (top) thermal resistance44.348.5
R θ JBJunction-to-board thermal resistance26.579.9
ψ JTJunction-to-top characterization parameter0.41.7
ψ JBJunction-to-board characterization parameter25.568.4
R θ JC(bot)Junction-to-case (bottom) thermal resistance46.2N/A

Typical Application

When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the RSET resistor from the SET pin to VREF to apply the offset and obtain the transfer function shown in Equation 6.

The desired output ranges for VDAC and VREF voltages determine the RSET and RG resistor values, calculated using Equation 7 and Equation 8. The system design requires a VDAC voltage range of 0.04 V to 4.96 V in order to operate the DAC8563 in the specified linear output range from codes 512 to 65 024.

IMON and IAOUT accomplish load monitoring. The sizing of RIMON and RIA determine the monitoring output voltage across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load current IDRV.

For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).

Related Variants

The following components are covered by the same datasheet.

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