DAC8562/883
a +5 Volt, Parallel Input Complete 12-Bit DAC
Digital-to-Analog Converter (DAC)Manufacturer
Analog Devices
Overview
Part: DAC8562, Analog Devices
Type: Complete 12-Bit DAC
Key Specs:
- Resolution: 12-Bit
- Supply Voltage: +5 V
- Full Scale Output Voltage: 4.095 V
- Resolution per Bit: 1 mV/Bit
- Output Drive Current: ±5 mA
- Typical Power Dissipation: 3 mW
- Reference Output Voltage: 2.5 V
- Operating Temperature Range: –40°C to +85°C
Features:
- No external components required
- Single +5 Volt operation
- True Voltage Output
- Very Low Power
- Includes rail-to-rail amplifier, latch, and reference on-chip
- Parallel input
- High speed digital interface
- Single CE signal
- Asynchronous CLR input
- Low temperature-coefficient silicon-chrome thin-film resistors
Applications:
- Digitally Controlled Calibration
- Servo Controls
- Process Control Equipment
- PC Peripherals
Package:
- 20-pin Plastic DIP: 74°C/W (Thermal Resistance)
- 20-Lead SOL-20 (SOIC): 89°C/W (Thermal Resistance)
Features
Complete 12-Bit DAC No External Components Single +5 Volt Operation 1 mV/Bit with 4.095 V Full Scale True Voltage Output, 65 mA Drive Very Low Power –3 mW
APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment PC Peripherals
Pin Configuration
Electrical Characteristics
| Parameter | Symbol | Condition | Min | Typ | Max | Units |
|---|---|---|---|---|---|---|
| STATIC PERFORMANCE Resolution Relative Accuracy | N INL | Note 2 E Grade F Grade | 12 –1/2 –1 | ±1/4 ±3/4 | +1/2 +1 | Bits LSB LSB |
| Differential Nonlinearity Zero-Scale |
NOTES
1 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2 1 LSB = 1 mV for 0 to +4.095 V output range.
3 Includes internal voltage reference error.
4 These parameters are guaranteed by design and not subject to production testing.
5 Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.
6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
Specifications subject to change without notice.
| Parameter | Symbol | Condition | Min | Typ | Max | Units |
|---|---|---|---|---|---|---|
| STATIC PERFORMANCE | ||||||
| Relative Accuracy | INL | –1 | ±3/4 | +1 | LSB | |
| Differential Nonlinearity | DNL | No Missing Codes | –1 | ±3/4 | + 1 | LSB |
| Zero-Scale Error | VZSE | Data = 000H | +1/2 | +3 | LSB | |
| Full-Scale Voltage | VFS | Data = FFFH | 4.085 | 4.095 | 4.105 | V |
| Reference Output Voltage | VREF | 2.490 | 2.500 | 2.510 | V | |
| LOGIC INPUTS | ||||||
| Logic Input Low Voltage | VIL | 0.8 | V | |||
| Logic Input High Voltage | VIH | 2.4 | V | |||
| Input Leakage Current | IIL | 10 | μA | |||
| SUPPLY CHARACTERISTICS | ||||||
| Positive Supply Current | IDD | VIH = 2.4 V, VIL = 0.8 V | 3 | 6 | mA | |
| VIL = 0 V, VDD = +5 V | 0.6 | 1 | mA | |||
| Power Dissipation | PDISS | VIH = 2.4 V, VIL = 0.8 V | 15 | 30 | mW | |
| VIL = 0 V, VDD = +5 V | 3 | 5 | mW | |||
| Power Supply Sensitivity | PSS | ∆VDD = ±5% | 0.002 | 0.004 | %/% |
Absolute Maximum Ratings
- Logic Inputs to DGND–0.3 V, VDD + 0.3 V
- VOUT to AGND–0.3 V, VDD + 0.3 V
- VREFOUT to AGND–0.3 V, VDD + 0.3 V
- AGND to DGND –0.3 V, VDD
- IOUT Short Circuit to GND 50 mA
- Package Power Dissipation (TJ max – TA)/uJA
- Thermal Resistance uJA
- 20-Pin Plastic DIP Package (P) 74°C/W
- 20-Lead SOIC Package (S) 89°C/W
- Maximum Junction Temperature (TJ max) 150°C
- Operating Temperature Range –40°C to +85°C
- Storage Temperature Range –65°C to +150°C
- Lead Temperature (Soldering, 10 secs) +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 2. Timing Diagram
Table I. Control Logic Truth Table
| CE | CLR | DAC Register Function |
|---|---|---|
| H | H | Latched |
| L | H | Transparent |
| ↑ + | H | Latched with New Data |
| X | L | Loaded with All Zeros |
| H | ↑ + | Latched All Zeros |
↑ + Positive Logic Transition; X Don't Care.
Related Variants
The following components are covered by the same datasheet.
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