ADF4351BCPZ

Wideband Synthesizer with Integrated VCO

The ADF4351BCPZ is a wideband synthesizer with integrated vco from Analog Devices Inc.. View the full ADF4351BCPZ datasheet below including key specifications.

Manufacturer

Analog Devices Inc.

Key Specifications

Parameter	Value
Differential - Input:Output	No/Yes
DigiKey Programmable	Not Verified
Divider/Multiplier	Yes/Yes
Frequency - Max	4.4GHz
Input	CMOS, TTL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature	-40°C ~ 85°C
Output	Clock
Package / Case	32-VFQFN Exposed Pad, CSP
PLL	Yes
Ratio - Input:Output	1:2
Supplier Device Package	32-LFCSP-VQ (5x5)
Type	Fanout Distribution, Fractional N, Integer N, Clock/Frequency Synthesizer (RF)
Supply Voltage	3V ~ 3.6V

Overview

Part: ADF4351 — Analog Devices Type: Wideband Synthesizer with Integrated VCO

Description: The ADF4351 is a fractional-N or integer-N phase-locked loop (PLL) frequency synthesizer with an integrated voltage controlled oscillator (VCO) providing a fundamental output frequency from 2200 MHz to 4400 MHz, and divided outputs down to 35 MHz.

Operating Conditions:

Supply voltage: 3.0 V to 3.6 V
Operating temperature: -40°C to +85°C
Reference input frequency: 10 MHz to 250 MHz

Absolute Maximum Ratings:

Max supply voltage (AVDD to GND): +3.9 V
Max junction temperature: 150°C
Storage temperature: -65°C to +125°C

Key Specs:

Output frequency range: 35 MHz to 4400 MHz
VCO output frequency: 2200 MHz to 4400 MHz (fundamental)
Typical jitter: 0.27 ps rms
Power supply current (DI DD + AI DD): 21 mA (typ), 27 mA (max)
VCO current (I VCO): 70 mA (typ), 80 mA (max)
Charge pump current (I CP): 5 mA (High Value), 0.312 mA (Low Value)
Normalized phase noise floor (PN SYNTH): -220 dBc/Hz (typ)
Minimum RF output power: -4 dBm (typ)
Maximum RF output power: 5 dBm (typ)

Features:

Fractional-N and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction

Applications:

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation

Package:

32-Lead LFCSP (CP-32-7)

Features

Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output Typical jitter: 0.3 ps rms Typical EVM at 2.1 GHz: 0.4% Power supply: 3.0 V to 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction

Applications

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

Pin Configuration

09800-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.	Mnemonic	Description
1	CLK	Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOSinput.
2	DATA	Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOSinput.
3	LE	Load Enable.When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is selected by the three control bits. This input is a high impedanceCMOS input.
4	CE	Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device, depending on the status of the power-down bits.
5	SW	Fast Lock Switch. Aconnection should be made from the loop filter to this pin when using the fast lock mode.
6	V P	Charge Pump Power Supply.V P must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible.
7	CP OUT	Charge Pump Output.When enabled, this output provides ±I CP to the external loop filter. The output of the loop filter is connected toV TUNE to drive the internal VCO.
8	CP GND	Charge Pump Ground. This output is the ground return pin for CP OUT .
9	AGND	Analog Ground. Ground return pin for AV DD .
10	AV DD	Analog Power Supply. This pin ranges from 3.0V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. AV DD must have the same value as DV DD .
11, 18, 21	A GNDVCO	VCO Analog Ground. Ground return pins for the VCO.
12	RF OUT A+	VCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available.
13	RF OUT A-	ComplementaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided- down version is available.
14	RF OUT B+	AuxiliaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available.
15	RF OUT B-	Complementary AuxiliaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available.
16, 17	V VCO	Power Supply for the VCO. This pin ranges from 3.0V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to these pins as possible.V VCO must have the same value as AV DD .
19	TEMP	Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as possible.
20	V TUNE	Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP OUT output voltage.

Pin No.	Mnemonic	Description
22	R SET	Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage bias at the R SET pin is 0.55 V. The relationship between I CP and R SET is as follows: I CP = 25.5/ R SET where: R SET = 5.1 kΩ. I CP = 5 mA.
23	V COM	Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane as close to this pin as possible.
24	V REF	Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible.
25	LD	Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss of PLL lock.
26	PDB RF	RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27	DGND	Digital Ground. Ground return pin for DV DD .
28	DV DD	Digital Power Supply. DV DD must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible.
29	REF IN	Reference Input. This CMOSinput has a nominal threshold of AV DD /2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30	MUXOUT	Multiplexer Output. The multiplexer output allows the lock detect value, the Ndivider value, or the R counter value to be accessed externally.
31	SD GND	Digital Σ-∆ Modulator Ground. Ground return pin for the Σ-∆ modulator.
32	SDV DD	Power Supply Pin for the Digital Σ-∆ Modulator. SDV DD must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible.
EP	Exposed Pad	Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.

Thermal Information

Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
ADF4351	Analog Devices Inc.	—
ADF4351BCPZ-RL7	Analog Devices Inc.	—

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