ADF4351
Wideband Fractional-N PLL Synthesizer with VCOThe ADF4351 is a wideband fractional-n pll synthesizer with vco from Analog Devices. View the full ADF4351 datasheet below including key specifications.
Official ADF4351 datasheet (PDF) — the source this page was extracted from.
ADF4351 Key Specifications
| Parameter | Value |
|---|---|
| Prescaler | Dual-modulus 4/5 or 8/9 |
| Typical Jitter | 0.3 ps rms |
| Output Dividers | 1/2/4/8/16/32/64 |
| Control Interface | 3-wire serial |
| Sleep Mode Current | 7 μA typ |
| VCO Supply Current | 70 mA typ |
| Charge Pump Current | 0.312 mA to 5 mA (RSET = 5.1 kΩ) |
| Logic Compatibility | 1.8V |
| Operating Temperature | -40°C to +85°C |
| Supply Voltage (AVDD) | 3.0V to 3.6V |
| Output Frequency Range | 35 MHz to 4400 MHz |
| Typical EVM At 2.1 GHz | 0.4% |
| RF Output Stage Current | 21 mA typ |
| Reference Input Frequency | 10 MHz to 250 MHz |
| VCO Fundamental Frequency | 2200 MHz to 4400 MHz |
| Supply Current (DIDD + AIDD) | 21 mA typ |
| Phase Detector Frequency (Integer-N) | 45 MHz (band select enabled), 90 MHz (disabled) |
| Phase Detector Frequency (Fractional-N) | 32 MHz max |
ADF4351 Overview
Part: ADF4351 — Analog Devices
Type: Wideband Synthesizer with Integrated VCO
Description: Fractional-N/integer-N wideband frequency synthesizer with integrated VCO covering 35 MHz to 4400 MHz from a 3.0 V to 3.6 V power supply.
Operating Conditions:
- Supply voltage: 3.0 V to 3.6 V
- Operating temperature: -40 °C to +85 °C
- RF output frequency range: 35 MHz to 4400 MHz (2200 MHz to 4400 MHz fundamental)
Absolute Maximum Ratings:
- Max supply voltage: 3.9 V (AVDD, VVCO to GND)
- Max junction/storage temperature: 150 °C junction / -65 °C to +125 °C storage
Key Specs:
- Reference input frequency: 10 MHz to 250 MHz
- Phase detector frequency: up to 32 MHz (Fractional-N), up to 90 MHz (Integer-N, band select disabled)
- Charge pump current (ICP): 0.312 mA to 5 mA (RSET = 5.1 kΩ)
- Supply current (DIDD + AIDD): 21 mA typ, 27 mA max
- VCO supply current (IVCO): 70 mA typ, 80 mA max
- RF output power: -4 dBm min to +5 dBm max (programmable in 3 dB steps)
- VCO phase noise (open-loop, 2.2 GHz carrier): -114 dBc/Hz at 100 kHz offset, -134 dBc/Hz at 1 MHz offset
- Normalized phase noise floor: -220 dBc/Hz (ABP = 6 ns), -221 dBc/Hz (ABP = 3 ns)
Features:
- Integrated VCO covering 2200 MHz to 4400 MHz
- Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output dividers
- Programmable dual-modulus prescaler of 4/5 or 8/9
- 3-wire serial interface (1.8 V logic compatible)
- Analog and digital lock detect
- RF output mute function (pin- and software-controllable)
- Auxiliary RF output
Applications:
- Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT)
- Test equipment
- Wireless LANs, CATV equipment
- Clock generation
Package:
- 32-lead LFCSP (CP-32-7)
ADF4351 Features
Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output Typical jitter: 0.3 ps rms Typical EVM at 2.1 GHz: 0.4% Power supply: 3.0 V to 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction
ADF4351 Applications
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation
ADF4351 Pin Configuration
09800-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
| Pin No. | Mnemonic | Description |
|---|---|---|
| 1 | CLK | Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOSinput. |
| 2 | DATA | Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOSinput. |
| 3 | LE | Load Enable.When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is selected by the three control bits. This input is a high impedanceCMOS input. |
| 4 | CE | Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device, depending on the status of the power-down bits. |
| 5 | SW | Fast Lock Switch. Aconnection should be made from the loop filter to this pin when using the fast lock mode. |
| 6 | V P | Charge Pump Power Supply.V P must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible. |
| 7 | CP OUT | Charge Pump Output.When enabled, this output provides ±I CP to the external loop filter. The output of the loop filter is connected toV TUNE to drive the internal VCO. |
| 8 | CP GND | Charge Pump Ground. This output is the ground return pin for CP OUT . |
| 9 | AGND | Analog Ground. Ground return pin for AV DD . |
| 10 | AV DD | Analog Power Supply. This pin ranges from 3.0V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. AV DD must have the same value as DV DD . |
| 11, 18, 21 | A GNDVCO | VCO Analog Ground. Ground return pins for the VCO. |
| 12 | RF OUT A+ | VCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available. |
| 13 | RF OUT A- | ComplementaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided- down version is available. |
| 14 | RF OUT B+ | AuxiliaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available. |
| 15 | RF OUT B- | Complementary AuxiliaryVCO Output. The output level is programmable.TheVCO fundamental output or a divided-down version is available. |
| 16, 17 | V VCO | Power Supply for the VCO. This pin ranges from 3.0V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to these pins as possible.V VCO must have the same value as AV DD . |
| 19 | TEMP | Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as possible. |
| 20 | V TUNE | Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP OUT output voltage. |
| Pin No. | Mnemonic | Description |
|---|---|---|
| 22 | R SET | Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage bias at the R SET pin is 0.55 V. The relationship between I CP and R SET is as follows: I CP = 25.5/ R SET where: R SET = 5.1 kΩ. I CP = 5 mA. |
| 23 | V COM | Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane as close to this pin as possible. |
| 24 | V REF | Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible. |
| 25 | LD | Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss of PLL lock. |
| 26 | PDB RF | RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable. |
| 27 | DGND | Digital Ground. Ground return pin for DV DD . |
| 28 | DV DD | Digital Power Supply. DV DD must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible. |
| 29 | REF IN | Reference Input. This CMOSinput has a nominal threshold of AV DD /2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. |
| 30 | MUXOUT | Multiplexer Output. The multiplexer output allows the lock detect value, the Ndivider value, or the R counter value to be accessed externally. |
| 31 | SD GND | Digital Σ-∆ Modulator Ground. Ground return pin for the Σ-∆ modulator. |
| 32 | SDV DD | Power Supply Pin for the Digital Σ-∆ Modulator. SDV DD must have the same value as AV DD . Place decoupling capacitors to the ground plane as close to this pin as possible. |
| EP | Exposed Pad | Exposed Pad. The LFCSP has an exposed pad that must be connected to GND. |
ADF4351 Thermal Information
Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADF4351BCPZ | Analog Devices | 32-VFQFN Exposed Pad, CSP |
| ADF4351BCPZ-RL7 | Analog Devices | LFCSP-32 5x5mm |
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All Integrated Circuits datasheetsAll Analog Devices datasheets (713)
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