ADF4351

Wideband Synthesizer with Integrated VCO

Manufacturer

Analog Devices Inc.

Overview

Part: ADF4351, Analog Devices

Type: Wideband Synthesizer with Integrated VCO

Key Specs:

Output frequency range: 35 MHz to 4400 MHz
Power supply: 3.0 V to 3.6 V
Integrated RMS Jitter: 0.27 ps
VCO fundamental output frequency: 2200 MHz to 4400 MHz
Maximum RF Output Power: 5 dBm
Minimum RF Output Power: -4 dBm
Operating temperature range: -40°C to +85°C

Features:

Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output
Typical EVM at 2.1 GHz: 0.4%
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
Auxiliary RF output

Applications:

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation

Package:

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Features

Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output Typical jitter: 0.3 ps rms Typical EVM at 2.1 GHz: 0.4% Power supply: 3.0 V to 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction

Applications

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

Pin Configuration

Table 5. Pin Function Descriptions

Pin No.	Mnemonic	Description
1	CLK	Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
2	DATA	Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input.
3	LE	Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is selected by the three control bits. This input is a high impedance CMOS input.
4	CE	Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device, depending on the status of the power-down bits.
5	SW	Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode.
6	VP	Charge Pump Power Supply. VP must have the same value as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible.
7	CPOUT	Charge Pump Output. When enabled, this output provides ±I CP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the internal VCO.
8	CPGND	Charge Pump Ground. This output is the ground return pin for CPOUT.
9	AGND	Analog Ground. Ground return pin for AVDD.
10	AVDD	Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. AVDD must have the same value as DVDD.
11, 18, 21	AGNDVCO	VCO Analog Ground. Ground return pins for the VCO.
12	RFOUTA+	VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is available.
13	RFOUTA-	Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
14	RFOUTB+	Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is available.
15	RFOUTB-	Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is available.
16, 17	VVCO	Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground plane as close to these pins as possible. VVCO must have the same value as AVDD.
19	TEMP	Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as possible.
20	VTUNE	Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT output voltage.

Pin No.	Mnemonic	Description
22	RSET	Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is as follows: ICP = 25.5/RSET where: RSET = 5.1 kΩ. ICP = 5 mA.
23	VCOM	Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane as close to this pin as possible.
24	VREF	Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible.
25	LD	Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss of PLL lock.
26	PDBRF	RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27	DGND	Digital Ground. Ground return pin for DVDD.
28	DVDD	Digital Power Supply. DVDD must have the same value as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible.
29	REFIN	Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30	MUXOUT	Multiplexer Output. The multiplexer output allows the lock detect value, the N divider value, or the R counter value to be accessed externally.
31	SDGND	Digital Σ-Δ Modulator Ground. Ground return pin for the Σ-Δ modulator.
32	SDVDD	Power Supply Pin for the Digital Σ-Δ Modulator. SDVDD must have the same value as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible.
EP	Exposed Pad	Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.

Absolute Maximum Ratings

TA = 25°C, unless otherwise noted.

Table 3.

Parameter	Rating
AVDD to GND1	-0.3 V to +3.9 V
AVDD to DVDD	-0.3 V to +0.3 V
VVCO to GND1	-0.3 V to +3.9 V
VVCO to AVDD	-0.3 V to +0.3 V
Digital I/O Voltage to GND1	-0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND1	-0.3 V to VDD + 0.3 V
REFIN to GND1	-0.3 V to VDD + 0.3 V
Operating Temperature Range	-40°C to +85°C
Storage Temperature Range	-65°C to +125°C
Maximum Junction Temperature	150°C
Reflow Soldering
Peak Temperature	260°C
Time at Peak Temperature	40 sec

¹ GND = AGND = DGND = CPGND = SDGND = AGNDVCO = 0 V.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

This device is a high performance RF integrated circuit with an ESD rating of <1.5 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT

The transistor count for the ADF4351 is 36,955 (CMOS) and 986 (bipolar).

THERMAL RESISTANCE

Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.

Table 4. Thermal Resistance

Package Type	θJA	Unit
32-Lead LFCSP (CP-32-7)	27.3	°C/W

ESD CAUTION

Thermal Information

Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
ADF4351BCPZ	Analog Devices Inc.	32-VFQFN Exposed Pad, CSP
ADF4351BCPZ-RL7	Analog Devices Inc.	—

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