ADE9000ACPZ-RL
Multiphase Energy and Power Quality Monitoring ICThe ADE9000ACPZ-RL is a multiphase energy and power quality monitoring ic from Analog Devices. View the full ADE9000ACPZ-RL datasheet below including absolute maximum ratings.
Manufacturer
Analog Devices
Category
Multiphase Energy and Power Quality Monitoring IC
Package
CP-40-7
Overview
Part: ADE9000 — Analog Devices Type: High Performance, Multiphase Energy, and Power Quality Monitoring IC Description: A highly accurate, fully integrated, multiphase energy and power quality monitoring device with 7 high-performance ADCs, 101 dB SNR, and ±25 ppm/°C maximum channel drift, enabling Class 0.2 metrology over a 10000:1 dynamic range.
Operating Conditions:
- Supply voltage: 2.97 V to 3.63 V
- Operating temperature: -40°C to +85°C
- CLKIN: 24.576 MHz crystal (XTAL)
Absolute Maximum Ratings:
- Max operating voltage on analog input pins (VxP, VxN, IxP, IxN): ±0.6 V
Key Specs:
- Total Active Energy Accuracy: 0.1% over 5000:1 dynamic range (10 sec accumulation)
- SNR (PGA=1): 101 dB (8 kSPS, sinc4 + IIR LPF output, VIN = -0.5 dB from FS)
- THD (PGA=1): -101 dB (8 kSPS, sinc4 + IIR LPF output, VIN = -0.5 dB from FS)
- Channel Drift (PGA, ADC, Internal VREF): ±25 ppm/°C max (PGA = 1, 2, or 4, internal VREF)
- Differential Input Voltage Range: ±1/Gain V (707 mV rms FS at gain = 1)
- SPI Communication Speed: 20 MHz
- Integrated Temperature Sensor Accuracy: ±3°C from -40°C to +85°C
- Internal Voltage Reference: 1.250 V (TA = 25°C)
Features:
- 7 high performance ADCs
- Wide input voltage range: ±1 V, 707 mV rms FS at gain = 1
- Power quality measurements (dip and swell monitors, line frequency, zero crossing, phase angle)
- Supports CTs and Rogowski coil (di/dt) sensors with digital integrator
- Flexible waveform buffer (resampling to 128 points per line cycle)
- Advanced metrology feature set (active power, VAR, VA, energies, RMS, THD, power factor)
- High speed communication port: 20 MHz serial port interface (SPI)
- Integrated temperature sensor with 12-bit SAR ADC
Applications:
- Energy and power monitoring
- Power quality monitoring
- Protective devices
- Machine health
- Smart power distribution units
- Polyphase energy meters
Package:
Features
- 7 high performance ADCs
- 101 dB SNR
- Wide input voltage range: ±1 V, 707 mV rms FS at gain = 1
- Differential inputs
- ±25 ppm/°C maximum channel drift (including ADC, internal VREF, PGA drift) enabling 10000:1 dynamic input range Class 0.2 metrology with standard external components
- Power quality measurements
- Enables implementation of IEC 61000-4-30 1
- VRMS ½, IRMS ½ rms voltage refreshed each half cycle
- 10 cycle rms/12 cycle rms
- Dip and swell monitors
- Line frequency-one per phase
- Zero crossing, zero-crossing timeout
- Phase angle measurements
- Supports CTs and Rogowski coil (di/dt) sensors
- Multiple range phase/gain compensation for CTs
- Digital integrator for Rogowski coils
- Flexible waveform buffer
- Able to resample waveform to ensure 128 points per line cycle for ease of external harmonic analysis
- Events, such as dip and swell, can trigger waveform storage
- Simplifies data collection for IEC 61000-4-7 harmonic analysis
- Advanced metrology feature set
- Total and fundamental active power, volt amperes reactive (VAR), volt amperes (VA), watthour, VAR hour, and VA hour
- Total and fundamental IRMS, VRMS
- Total harmonic distortion
- Power factor
- Supports active energy standards: IEC 62053-21 and IEC 62053-22; EN50470-3; OIML R46; and ANSI C12.20
- Supports reactive energy standards: IEC 62053-23, IEC 62053-24
- High speed communication port: 20 MHz serial port interface (SPI)
- Integrated temperature sensor with 12-bit successive approximation register (SAR) ADC
- ±3°C accuracy from -40°C to +85°C
1 For IEC 61000-4-30 Class S implementation, refer to the ADE9430 IC data sheet.
Applications
- Energy and power monitoring
- Power quality monitoring
- Protective devices
- Machine health
- Smart power distribution units
- Polyphase energy meters
Pin Configuration
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
| Pin No. | Mnemonic | Description |
|---|---|---|
| 1 | PULL_HIGH | Pull High. Tie this pin to VDD. |
| 2 | DGND | Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9000. Because the digital return currents in the ADE9000 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. |
| 3 | DVDDOUT | 1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor. |
| 4 | PM0 | Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground PM0 and PM1. |
| 5 | PM1 | Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0 and PM1. |
| 6 | RESET | Reset Input, Active Low. This pin must stay low for at least 1 μs to trigger a hardware reset. |
| 7, 8 | IAP, IAN | Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 9, 10 | IBP, IBN | Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 11, 12 | ICP, ICN | Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 13, 14 | INP, INN | Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 15 | REFGND | Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. |
| 16 | REF | Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V. An external reference source of 1.2 V to 1.25 V can also be connected at this pin. In either case, decouple REF to REFGND with 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor. After reset, the on-chip reference is enabled. To use the internal voltage reference with external circuits, a buffer is required. |
| 17 | NC1 | No Connection. It is recommended to tie this pin to ground. |
| 18 | NC2 | No Connection. It is recommended to tie this pin to ground. |
| 19, 20 | VAN, VAP | Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 21, 22 | VBN, VBP | Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 23, 24 | VCN, VCP | Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. |
| 25 | AVDDOUT | 1.9 V Output of the Analog Low Dropout Regulator (LDO). Decouple AVDDOUT with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor. Do not connect external active circuitry to this pin. |
| 26 | AGND | Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. |
Absolute Maximum Ratings
TA = 25°C, unless otherwise noted.
| Table 3. | Rating |
|---|---|
| VDD to GND | -0.3 V to +3.96 V |
| Analog Input Voltage to GND, IAP, IAN, IBP, IBN, ICP, ICN, INP, INN, VAP, VAN, VBP, VBN, VCP, VCN | -2 V to +2 V |
| Reference Input Voltage to REFGND | -0.3 V to +2 V |
| Digital Input Voltage to GND | -0.3 V to VDD + 0.3 V |
| Digital Output Voltage to GND | -0.3 V to VDD + 0.3 V |
| Operating Temperature | |
| Industrial Range | -40°C to +85°C |
| Storage Temperature Range | -65°C to +150°C |
| Junction Temperature | 125°C |
| Lead Temperature (Soldering, 10 sec) 1 | 260°C |
| ESD | |
| Human Body Model 2 | 4 kV |
| Machine Model 3 | 300 V |
| Field Induced Charged Device Model (FICDM) 4 | 1.25 kV |
1 Analog Devices recommends that reflow profiles used in soldering RoHS compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard.
2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of JEDEC).
4 Applicable standard: JESD22-C101F (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Thermal Information
Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.
θ JA and θ JC are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Typical Application
Figure 1. Typical Applications Circuit
VDD = 2.97 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 24.576 MHz crystal (XTAL), T MIN to T MAX = -40°C to +85°C, TA = 25°C (typical), unless otherwise noted.
Table 1.
- Parameter Min Typ Max Unit Test Conditions/Comments
- ACCURACY (MEASUREMENT ERROR PER PHASE)
- Total Active Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation
- 0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation
- 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, high-pass filter (HPF) corner = 4.98 Hz
- 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Total Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation
- 0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation
- 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Total Apparent Energy 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation
- 0.5 % Over a dynamic range of 5000 to 1, 10 sec accumulation
- 0.1 % Over a dynamic range of 500 to 1, 1 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.5 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Fundamental Active Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
- 0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
- 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Fundamental Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
- 0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
Table 1. (Continued)
- Parameter Min Typ Max Unit Test Conditions/Comments
- 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Fundamental Apparent Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
- 0.5 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
- 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.5 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz
- IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1
- 0.5 % Over a dynamic range of 5000 to 1
- 0.1 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.5 % Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Fundamental IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1
- 0.5 % Over a dynamic range of 5000 to 1
- 0.1 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.5 % Over a dynamic range of 2000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Active Power, VAR, VA 0.2 % Over a dynamic range of 1000 to 1
- 0.4 % Over a dynamic range of, 3000 to 1
- 0.2 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- 0.5 % Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz
- Power Factor (PF) Error ±0.001 % Over a dynamic range of 5000 to 1
- 128-Point per Line Cycle Resampled Data 0.1 % An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and ninth harmonic both at half of full scale (FS)
- -72 dB Amplitude of highest spur; input signal is 50 Hz fundamental and ninth harmonic both at half of FS
- 1.25 % An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and 31 st harmonic, both at half of FS
- -38 dB Amplitude of highest spur; input signal is
Table 1. (Continued)
| Parameter | Min | Typ | Max | Unit | Test Conditions/Comments |
|---|---|---|---|---|---|
| 50 Hz fundamental and 31 st harmonic, both at half of FS | |||||
| VRMS½, IRMS½ RMS Voltage | 0.25 | % | Data sourced before HPF, no dc offset at | ||
| Refreshed Each Half-Cycle 1 | inputs, over a dynamic range of 100 to 1 | ||||
| 10 Cycle/12 Cycle IRMS, VRMS 1 | 0.2 | % | Data sourced before HPF, no dc offset at inputs, over a dynamic range of 100 to 1 | ||
| Line Period Measurement | 0.001 | Hz | Resolution at 50 Hz | ||
| Current to Current, Voltage to Voltage, and Voltage to Current Angle Measurement | 0.018 | Degrees | Resolution at 50 Hz | ||
| ADC | |||||
| PGA Gain Settings (PGA_GAIN) | 1, 2, or 4 | V/V | PGA gain setting is referred to as PGA_GAIN | ||
| Differential Input Voltage Range (VxP to VxN, IxP to IxN) | -1/Gain | +1/Gain | V | 707 mV rms, when V REF = 1.25 V, this voltage corresponds to 53 million codes | |
| Maximum Operating Voltage on Analog Input Pins (VxP, VxN, IxP, and IxN) | -0.6 | +0.6 | V | Voltage on the pin with respect to ground | |
| Signal-to-Noise Ratio (SNR) 2 | |||||
| PGA = 1 | 96 | dB | 32 kSPS, sinc4 output, V IN = -0.5 dB from FS | ||
| 101 | dB | 8 kSPS, sinc4 + infinite impulse response (IIR), low-pass filter (LPF) output, V IN = -0.5 dB from FS | |||
| PGA = 4 | 93 | dB | 32 kSPS, sinc4 output | ||
| 96 | dB | 8 kSPS, sinc4 + IIR LPF output | |||
| Total Harmonic Distortion (THD) 2 PGA = 1 | -101 | -95 | dB | 32 kSPS, sinc4 output, V IN = -0.5 dB from FS | |
| -101 | -95 | dB | 8 kSPS, sinc4 + IIR LPF output, V = -0.5 dB from FS | ||
| PGA = 4 | -107 | -99 | dB | IN 32 kSPS, sinc4 output | |
| -107 | -99 | dB | 8 kSPS, sinc4 + IIR LPF output | ||
| Signal-to-Noise and Distortion Ratio (SINAD) 2 | |||||
| PGA = 1 | 95 | dB | 32 kSPS, sinc4 output, V IN = -0.5 dB from FS | ||
| 98 | dB | 8 kSPS, sinc4 + IIR LPF output, V IN = -0.5 dB from FS | |||
| PGA = 4 | 93 | dB | 32 kSPS, sinc4 output | ||
| Spurious-Free Dynamic Range (SFDR) 2 | |||||
| PGA = 1 | 100 | dB | 32 kSPS, sinc4 output, V IN = -0.5 dB from FS | ||
| 100 | dB | 8 kSPS, sinc4 + IIR LPF output, V = -0.5 dB from FS | |||
| Sinc4 Outputs | |||||
| 1.344 | kHz | 32 kSPS, sinc4 output | |||
| Sinc4 + IIR LPF Outputs | 1.344 | kHz | 8 kSPS output | ||
| Output Bandwidth (-3 dB) 2 | |||||
| Sinc4 Outputs | 7.2 | kHz | 32 kSPS, sinc4 output | ||
| Sinc4 + IIR LPF Outputs | 3.2 | kHz | 8 kSPS output | ||
| Crosstalk 2 | -120 | dB | At 50 Hz or 60 Hz, see the Terminology section | ||
| AC Power Supply Rejection Ratio | -120 | dB | At 50 Hz, see the Terminology section | ||
| (AC PSRR) 2 |
| Parameter | Min | Typ | Max | Unit | Test Conditions/Comments |
|---|---|---|---|---|---|
| Common-Mode Rejection Ratio (AC CMRR) 2 | 115 | dB | At 100 Hz and 120 Hz | ||
| Gain Error | ±0.3 | ±1 | %typ | See the Terminology section | |
| Gain Drift 2 | ±3 | ppm/°C | See the Terminology section | ||
| Offset | ±0.040 | ±3.8 | mV | See the Terminology section | |
| Offset Drift 2 | 0 | ±2 | μV/°C | See the Terminology section | |
| Channel Drift (PGA, ADC, Internal | ±7 | ±25 | ppm/°C | PGA = 1, internal V REF | |
| Voltage Reference) | |||||
| ±7 | ±25 | ppm/°C | PGA = 2, internal V REF | ||
| ±7 | ±25 | ppm/°C | PGA = 4, internal V REF | ||
| Differential Input Impedance (DC) | 165 | 185 | kΩ | PGA = 1, see the Terminology section | |
| 80 | 90 | kΩ | PGA = 2 | ||
| 40 | 45 | kΩ | PGA = 4 | ||
| INTERNAL VOLTAGE REFERENCE | Nominal = 1.25 V ± 1 mV | ||||
| Voltage Reference | 1.250 | V | T A = 25°C, REF pin | ||
| Temperature Coefficient 2 | ±5 | ±20 | ppm/°C | T A = -40°C to +85°C, tested during device | |
| Input Impedance | |||||
| Input Voltage (REF) | 1.2 or 1.25 | V | REFGND must be tied to GND, AGND, and DGND, a 1.25 V external reference is preferred; the FS values mentioned in this data sheet are for a | ||
| 7.5 | kΩ | voltage reference of 1.25 V | |||
| TEMPERATURE SENSOR | |||||
| Temperature Accuracy | ±2 | °C | -10°C to +40°C | ||
| ±3 | °C | -40°C to +85°C | |||
| Temperature Readout Step Size | 0.3 | °C | |||
| CRYSTAL OSCILLATOR | All specifications use CLKIN = 24.576 MHz ± 30 ppm | ||||
| Input Clock Frequency | 24.33 | 24.576 | 24.822 | MHz | |
| Internal Capacitance on CLKIN, CLKOUT | 4 | pF | |||
| Internal Feedback Resistance Between CLKIN and | 2.45 | MΩ | |||
| CLKOUT | |||||
| Transconductance (g m ) | 5 | 8 | mA/V | ||
| EXTERNAL CLOCK INPUT Input Clock Frequency Duty Cycle 2 | 24.330 45:55 | 24.576 50:50 | 24.822 55:45 | MHz % | ±1% |
| CLKIN Logic Input Voltage | 3.3 V tolerant | ||||
| High, V INH | 1.2 | V | V DD = 2.97 V to 3.63 | ||
| 0.5 | V | V V DD = 2.97 V to 3.63 V | |||
| Low, V INL | |||||
| LOGIC INPUTS (PM0, PM1, RESET, MOSI, | |||||
| SCLK, and SS) Input Voltage | |||||
| V INH | 2.4 | 0.8 | V | ||
| V INL Input Current, I IN | 15 | V μA | V IN = 0 V | ||
| Internal Capacitance, C IN | 10 | pF | |||
| LOGIC OUTPUTS |
| Parameter | Min | Typ | Max | Unit | Test Conditions/Comments |
|---|---|---|---|---|---|
| MISO, IRQ0, and IRQ1 | |||||
| Output Voltage | |||||
| High, V OH | 2.4 | V | I SOURCE = 4 mA | ||
| Low, V OL | 0.8 | V | I SINK = 4 mA | ||
| Internal Capacitance, C IN | 10 | pF | |||
| C1, CF2, CF3, and CF4 | |||||
| Output Voltage | |||||
| V OH | 2.4 | V | I SOURCE = 7 mA | ||
| V OL | 0.8 | V | I SINK = 8 mA | ||
| C IN | 10 | pF | |||
| LOW DROPOUT REGULATORS (LDOs) | |||||
| AVDD | 1.9 | V | |||
| DVDD | 1.7 | V | |||
| POWER SUPPLY | |||||
| V DD | 2.97 | 3.3 | 3.63 | V | Power-on reset level is 2.4 V to 2.6 V |
| Supply Current (V DD ) | |||||
| Power Save Mode 0 (PSM0) | 15 | 17 | mA | Normal mode | |
| 14.5 | 16.5 | mA | Normal mode, six ADCs enabled | ||
| Power Save Mode 3 (PSM3) | 90 | 300 | nA | Idle, V DD = 3.3 V, AV DD = 0 V, DV DD = 0 V |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADE9000 | Analog Devices | CP-40-71 |
| ADE9000ACPZ | Analog Devices | — |
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