AD9864-EBZ

Part: AD9864BCPZ — Analog Devices

Type: IF Digitizing Subsystem (band-pass Σ-Δ ADC receiver)

Description: 10–300 MHz IF input, 6.8–270 kHz output bandwidth IF digitizing subsystem with LNA, mixer, band-pass Σ-Δ ADC, decimation filter, 7.5 dB typical SSB noise figure and 17 mA typical operating current from a 2.7–3.6 V supply.

Operating Conditions:

• Supply voltage: 2.7–3.6 V (analog and digital); charge pump supplies VDDP/VDDQ 2.7–5.5 V; interface supply VDDH 1.8–3.6 V
• Operating temperature: -40 to +85 °C
• ADC clock frequency: 13–26 MHz; decimation factor 48–960

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI vs. ground); 6.0 V for VDDP, VDDQ
• Max junction temperature: 150 °C
• Storage temperature: -65 to +150 °C
• Max lead temperature: 300 °C

Key Specs:

• SSB noise figure: 7.5 dB typ, 9.5 dB max (minimum VGA attenuation); 13 dB typ at maximum attenuation
• Input IP3: -7.0 dBm typ (-12 dBm min)
• Dynamic range with AGC enabled: 95 dB typ (91 dB min)
• IF input clip point: -31 dBm typ at minimum VGA attenuation; -19 dBm typ at maximum attenuation
• LNA input impedance: 370 Ω || 1.4 pF
• AGC gain range: 12 dB; programmable gain step 16 dB
• Total current: 17 mA typ in operation; 0.01 mA typ in standby
• ADC alias attenuation: 80 dB min; decimator alias attenuation 88 min
• SPI clock: 10 MHz max
• Thermal resistance θJA: 29.5 °C/W (48-lead LFCSP)

Features:

• 10 MHz to 300 MHz input frequency
• 6.8 kHz to 270 kHz output signal bandwidth
• AGC free range up to -34 dBm; 12 dB continuous AGC range
• 16 dB front-end attenuator
• Baseband I/Q 16-bit (or 24-bit) serial digital output
• LO and sampling clock synthesizers
• Programmable decimation factor, output format, AGC and synthesizer settings via SPI
• Power-down mode via serial interface

Applications:

• Multimode narrow-band radio products
• Analog/digital UHF/VHF FDMA receivers
• TETRA, APCO25, GSM/EDGE
• Portable and mobile radio products
• SATCOM terminals

Package:

• 48-lead LFCSP

10 MHz to 300 MHz input frequency 6.8 kHz to 270 kHz output signal bandwidth 7.5 dB single sideband noise figure (SSB NF) -7.0 dBm input third-order intercept (IIP3) AGC free range up to -34 dBm 12 dB continuous AGC range 16 dB front -end attenuator Baseband I/Q 16-bit (or 24-bit) serial digital output LO and sampling clock synthesizers Programmable decimation factor, output format, AGC, and synthesizer settings 370 Ω input impedance 2.7 V to 3.6 V supply voltage Low current consumption: 17 mA 48-lead LFCSP package

Multimode narrow-band radio products Analog/digital UHF/VHF FDMA receivers TETRA, APCO25, GSM/EDGE Portable and mobile radio products SATCOM terminals

1 Protected by U.S. Patent No. 5,969,657; other patents pending.

04319-0-002

Figure 2. 48-Lead LFCSP Pin Configuration

Figure 2. 48-Lead LFCSP Pin Configuration

Table 5. 48-Lead Lead Frame Chip Scale Package (LFCSP) Pin Function Descriptions

Table 3. AD9864 Absolute Maximum Ratings Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

θ JA is specified for the worst-case conditions, that is, θ JA is specified for device soldered in circuit board for surface-mount packages.