efr32fg28_datasheet

Part: EFR32FG28 Wireless SoC Family

Type: Wireless System-on-Chip (SoC)

Key Specs:

• Core: 32-bit ARM Cortex-M33 with 78 MHz maximum operating frequency
• Flash Memory: Up to 1024 kB
• RAM Data Memory: Up to 256 kB
• Sub-GHz TX Power: Up to +20 dBm
• BLE TX Power: Up to +10 dBm
• Operating Voltage: 1.71 V to 3.8 V
• Operating Temperature: -40 °C to +125 °C
• GPIO: Up to 49
• ADC: 12-bit @ 1 Msps, 16-bit @ 76.9 ksps

Features:

• Dual band Sub-GHz + 2.4 GHz BLE radio
• Integrated Power Amplifiers (PAs)
• Matrix Vector Processor for AI/ML acceleration
• Low active and sleep currents
• DSP instruction and floating-point unit
• Preamble Sense Mode (PSM)
• Robust peripheral set including ADC, ACMP, VDAC, LESENSE, DMA, PRS, Timers, RTC, PCNT, Watchdog, EUSART, UART/SPI/SmartCard/IrDA/I2S, I2C, LCD Controller, Keypad scanner, Die temperature sensor
• Protocol Support: Proprietary, CONNECT, Amazon Sidewalk, WM-BUS, Wi-SUN, Bluetooth Low Energy
• Secure Vault with Hardware Cryptographic Acceleration (AES128/192/256, ChaCha20-Poly1305, SHA-1, SHA-2/256/384/512, ECDSA +ECDH, Ed25519 and Curve25519, J-PAKE, PBKDF2), True Random Number Generator (TRNG), ARM TrustZone, Secure Boot, Secure Debug Unlock, DPA Countermeasures, Secure Key Management with PUF, Anti-Tamper, Secure Attestation

Applications:

• Internet of Things (IoT)
• Smart homes
• Security
• Lighting
• Building automation
• Metering
• Home and Building Automation and Security
• Industrial Automation
• Street Lighting

Package:

• QFN68: 8 mm × 8 mm × 0.85 mm
• QFN48: 6 mm × 6 mm × 0.85 mm

• 32-bit ARM® Cortex®-M33 core with 78 MHz maximum operating frequency
• 1024 kB of flash and up to 256 kB of RAM
• Energy-efficient radio core with low active and sleep currents
• Integrated PAs with up to 20 dBm for sub-GHz and 10 dBm for BLE transmit power
• Robust peripheral set and up to 49 GPIO
• QFN48 and QFN68 package options Metering

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on TA=25 °C and all supplies at 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32FG28 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32FG28 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
  • In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
  • In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Note:

1. When operating as an LCD driver, the output voltage on a GPIO may safely exceed this specification. The pin output voltage may be up to 3.8 V in this case.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

Table 7.1. QFN48 Package Dimensions

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MS-013, Variation AA.

4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.

7.2 QFN48 PCB Land Pattern

Figure 7.2. QFN48 PCB Land Pattern Drawing

Dimension Typ

• 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
• 1. The stencil thickness should be 0.101 mm (4 mils).
• 1. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
• 1. A 3x3 array of 1.10mm x 1.10mm openings on 1.30mm pitch should be used for the center ground pad.
• 1. A No-Clean, Type-3 solder paste is recommended.
• 1. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
• 1. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling.

7.3 QFN48 Package Marking

Figure 7.3. QFN48 Package Marking

The package marking consists of:

• FFFF The product family codes.
  • 1. Family Code ( F | Z )
  • 1. G (Gecko)
  • 1. Series (2)
  • 1. Device Configuration (8)
• PPP The product option codes.
  • 1-2. Feature codes [f2, f3] (RF configuration)
    • 10 = Two 14 dBm Sub-GHz PAs
    • 12 = One 14 dBm Sub-GHz PA and One 10 dBm BLE 2.4 GHz PA
    • 20 = Two 20 dBm Sub-GHz PAs
    • 22 = One 20 dBm Sub-GHz PA and One 10 dBm BLE 2.4 GHz PA
  • 1. Flash ( J = 1024k )
• TTTTTT A trace or manufacturing code. The first letter is the device revision.
• YY The last 2 digits of the assembly year.
• WW The 2-digit workweek when the device was assembled.