adf4383
[ADF4383](https://www.analog.com/ADF4383)
The adf4383 is an electronic component. [ADF4383](https://www.analog.com/ADF4383). View the full adf4383 datasheet below including absolute maximum ratings.
Overview
Part: ADF4383, Analog Devices
Type: Microwave Wideband Synthesizer with Integrated VCO / Fractional-N Phased-Locked Loop (PLL)
Key Specs:
- VCO frequency range: 10 GHz to 20 GHz
- Integrated RMS jitter at 20 GHz: 18 fs (integration bandwidth: 100 Hz to 100 MHz)
- VCO fast calibration time: <2 μs
- Phase noise floor: -156 dBc/Hz at 20 GHz
- Normalized in-band phase noise floor (integer mode): -239 dBc/Hz
- Maximum phase/frequency detector input frequency: 625 MHz
- Reference input frequency: 10 MHz to 4500 MHz
- Operating temperature: -40°C to +105°C
- Power supplies: 3.3 V and 5 V
Features:
- VCO phase noise improvement of up to 3 dB as compared to ADF4382
- Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
- VCO autocalibration time: <100 μs
- Normalized 1/f phase noise floor: -287 dBc/Hz
- Typical spurious fPFD: -90 dBc
- Propagation delay temperature coefficient: 0.06 ps/°C
- Adjustment step size: <1 ps
- Multichip output phase alignment
- ADIsimPLL™ loop filter design tool support
- Output dividers allow complete output frequency range from 625 MHz to 20 GHz
- Automatically aligns output to input reference edge
- Programmable reference to output delay with <1 ps resolution
- Simplified serial peripheral interface (SPI) register map
- External SYNC input
- Repeatable multichip alignment in both integer and fractional mode
Applications:
- High performance data converter clocking
- Wireless infrastructure (MC-GSM, 5G, 6G)
- Test and measurement
Package:
- 48-terminal LGA: 7 mm × 7 mm
Features
- ► Fundamental VCO frequency range: 10 GHz to 20 GHz
- ► VCO phase noise improvement of up to 3 dB as compared to ADF4382
- ► Integrated RMS jitter at 20 GHz = 18 fs (integration bandwidth: 100 Hz to 100 MHz)
- ► Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
- ► VCO fast calibration time: <2 μs
- ► VCO autocalibration time: <100 μs
- ► Phase noise floor: -156 dBc/Hz at 20 GHz
- ► PLL specifications
- ► -239 dBc/Hz: normalized in-band phase noise floor (integer mode)
- ► -287 dBc/Hz: normalized 1/f phase noise floor
- ► 625 MHz maximum phase/frequency detector input frequency
- ► 4.5 GHz reference input frequency
- ► Typical spurious fPFD: -90 dBc
- ► Reference to output delay specifications
- ► Propagation delay temperature coefficient: 0.06 ps/°C
- ► Adjustment step size: <1 ps
- ► Multichip output phase alignment
- ► 3.3 V and 5 V power supplies
- ► ADIsimPLL™ loop filter design tool support
- ► 7 mm × 7 mm, 48-terminal LGA
- ► -40°C to +105°C operating temperature
Applications
- ► High performance data converter clocking
- ► Wireless infrastructure (MC-GSM, 5G, 6G)
- ► Test and measurement
Pin Configuration
Table 6. Pin Function Descriptions
| Pin No. | Mnemonic | Description |
|---|---|---|
| 1, 2, 4, 10, 12, 14, 16, 18, 19, 21, 23, 25, 26, 41, 48 | GND | Negative Power Supply (Ground). Tie the GND pins directly to the ground pad. |
| 3 | V3_NDIV | 3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short the V3_NDIV pin to the other pins in the 3.3 V Power Supply Group 1. |
| 5 | V3_VCOB | 3.15 V to 3.45 V Positive Power Supply Pin for the Bias Circuitry and Digital Logic Control Portion of the VCO. Short the V3_VCOB pin to the other pins in the 3.3 V Power Supply Group 2. |
| 6 | VG_BIAS | Bias Decoupling Pin. Connect uninstalled 0402, 0.1 μF capacitor footprint to GND. |
| 7 | VTUNE | VCO Tuning Input. This frequency control pin is normally connected to the external loop filter. |
| 8 | V5_CAL | 4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. The V5_CAL pin can be shorted to the V5_VCO supply plane. |
| 9 | V5_VCO | 4.75 V to 5.25 V Positive Power Supply Pin for the VCO Circuitry. |
| 11 | V3_OUTDIV | 3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short the V3_OUTDIV pin to the other pins in the 3.3 V Power Supply Group 2. |
| 13 | V3_RFOUT2 | 3.15 V to 3.45 V Positive Power Supply Pin for the RFOUT 2 Buffer Circuitry. Short the V3_RFOUT2 pin to the other pins in the 3.3 V Power Supply Group 2. |
| 15, 17 | RFOUT2N, RFOUT2P | RF Output 2 Output Signal. The VCO output divider is buffered and presented differentially on the RFOUT2N and RFOUT2P pins. The outputs have a 50 Ω (typical) output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the outputs. The output amplitude is programmable via the serial port. |
| 20, 22 | RFOUT1N, RFOUT1P | RF Output 1 Output Signal. The VCO output divider is buffered and presented differentially on the RFOUT1N and REFOUT1P pins. The outputs have 50 Ω (typical) output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the outputs. The output amplitude is programmable via the serial port. |
| 24 | V3_RFOUT1 | 3.15 V to 3.45 V Positive Power Supply Pin for the RFOUT 1 Buffer Circuitry. Short the V3_RFOUT1 pin to the other pins in the 3.3 V Power Supply Group 2. |
| 27 | LKDET | PLL Lock Detect. This output presents the lock status of the PLL. The PLL is locked when LKDET is a logic high. |
| 28 | DELADJ | Delay Adjust Input Signal. Logic 0 ensures that the delay of the RF output signal is reduced after DELSTR is asserted. Logic 1 ensures that the delay of the RF output signal is increased after DELSTR is asserted. |
| 29 | DELSTR | Delay Strobe Input Signal. A rising edge on this signal indicates that an adjustment is needed. The adjustment is then made on the falling edge. |
| 30 | V3_LS | 3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short the V3_LS pin to the other pins in the 3.3 V Power Supply Group 1. |
| 31 | CE | Chip Enable. 3.3 V CMOS input. Does not support 1.8 V CMOS levels. This CMOS input enables the device when driven high. A logic low disables the device, putting the device in a full power-down state causing the register to reset. Conversely, the PD_ALL bit powers down the device, but does not reset the registers. |
Absolute Maximum Ratings
TA = 25°C, unless otherwise noted.
Table 3. Absolute Maximum Ratings
| Parameter | Rating |
|---|---|
| V3.3V_1 (V3_LS, V3_LDO, V3_REF, V3_PFD, and V3_NDIV) to GND | -0.3 V to +3.6 V |
| V3.3V_2 (V3_VCO, V3_OUTDIV, V3_RFOUT1, and V3_FOUT2) to GND | -0.3 V to +3.6 V |
| VV5_CAL, VV5_VCO, and VV5_CP to GND | -0.3 V to +5.5 V |
| Voltage on CP Pin | -0.3 V to V5_CP + 0.3 V |
| Voltage on All Other Pins | -0.3 V to V3.3V_1 + 0.3 V |
| Digital Outputs (MUXOUT, LKDET, SDO, and SDIO) | 5 mA |
| RFOUT1P/RFOUT1N and RFOUT2P/RFOUT2N | Maximum (GND - 0.3 V, |
| V3.3V_2 - 1.2 V) to V3.3V_2 + 0.3 V | |
| REFP and REFN | -0.65 V to V3.3V_1 + 0.65 V |
| Voltage on all Other Pins | -0.3 V to V3.3V_1 + 0.3 V |
| REFP to REFN and SYNCP to SYNCN | ±1.35 V |
| Temperature | |
| Operating Junction Range | -40°C to +125°C |
| Storage Range | -55°C to +150°C |
| Maximum Junction | 150°C |
| Reflow Soldering | |
| Peak Temperature | 260°C |
| Time at Peak Temperature | 30 sec |
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Thermal Information
Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θJC-TOP and θJC-BOTTOM are the junction-to-case thermal resistance top and bottom.
Table 4. Thermal Resistance
| Package Type1 | θJA | θJC-TOP | θJC-BOTTOM | Unit |
|---|---|---|---|---|
| CC-48-10 | 25.23 | 16.11 | 5.10 | °C/W |
1 Test Condition 1: thermal impedance simulated values are based on use of a 4-layer PCB with the thermal impedance paddle soldered to a ground plane.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADF4383BCCZ | Analog Devices | — |
| ADF4383BCCZ-RL7 | Analog Devices | — |
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