ADF4383BCCZ

Part: ADF4383 — Analog Devices Type: Microwave Wideband Synthesizer with Integrated VCO Description: A high performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) generating frequencies from 625 MHz to 20 GHz, featuring 18 fs integrated RMS jitter at 20 GHz and a -156 dBc/Hz phase noise floor.

Operating Conditions:

• Supply voltage: 3.15–3.45 V (3.3V supplies), 4.75–5.25 V (5V supplies)
• Operating temperature: -40°C to +105°C
• VCO fundamental frequency range: 10 GHz to 20 GHz
• Maximum phase/frequency detector input frequency: 625 MHz

Absolute Maximum Ratings:

• Max supply voltage (3.3V supplies): +3.6 V
• Max supply voltage (5V supplies): +5.5 V
• Max digital output current: 5 mA
• Max junction temperature: 150°C
• Max storage temperature: -55°C to +150°C

Key Specs:

• Integrated RMS jitter: 18 fs (100 Hz to 100 MHz integration bandwidth, RFOUT = 20 GHz)
• VCO autocalibration time: 100 μs
• Phase noise floor: -156 dBc/Hz (RFOUT = 20 GHz)
• Normalized in-band phase noise floor (Integer Mode): -239 dBc/Hz
• Normalized 1/f phase noise floor: -287 dBc/Hz
• Reference input frequency: 10 MHz to 4500 MHz
• RF output frequency: 0.625 GHz to 20 GHz
• Differential RF output power: 9 dBm (f OUT = 14 GHz, RFOUT_OPWR = 11)
• Propagation delay temperature coefficient: 0.06 ps/°C

Features:

• VCO phase noise improvement of up to 3 dB vs. ADF4382
• VCO fast calibration time: <2 μs
• Multichip output phase alignment
• Programmable reference to output delay with <1 ps resolution
• ADIsimPLL™ loop filter design tool support
• Simplified serial peripheral interface (SPI) register map

Applications:

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement

Package:

• 7 mm × 7 mm, 48-terminal LGA (CC-48-10)

• Fundamental VCO frequency range: 10 GHz to 20 GHz
• VCO phase noise improvement of up to 3 dB as compared to ADF4382
• Integrated RMS jitter at 20 GHz = 18 fs (integration bandwidth: 100 Hz to 100 MHz)
• Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
• VCO fast calibration time: <2 μs
• VCO autocalibration time: <100 μs
• Phase noise floor: -156 dBc/Hz at 20 GHz
• PLL specifications
• -239 dBc/Hz: normalized in-band phase noise floor (integer mode)
• -287 dBc/Hz: normalized 1/f phase noise floor
• 625 MHz maximum phase/frequency detector input frequency
• 4.5 GHz reference input frequency
• Typical spurious f PFD : -90 dBc
• Reference to output delay specifications
• Propagation delay temperature coefficient: 0.06 ps/°C
• Adjustment step size: <1 ps
• Multichip output phase alignment
• 3.3 V and 5 V power supplies
• ADIsimPLL ™ loop filter design tool support
• 7 mm × 7 mm, 48-terminal LGA
• -40°C to +105°C operating temperature

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement

Figure 1. ADF4383 Functional Block Diagram

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

TA = 25°C, unless otherwise noted.

Table 3. Absolute Maximum Ratings

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.

θ JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θ JC-TOP and θ JC-BOTTOM are the junction-to-case thermal resistance top and bottom.

Table 4. Thermal Resistance