ADF4383BCCZ

Part: ADF4383 — Analog Devices

Type: Microwave Wideband Synthesizer with Integrated VCO

Description: Fractional-N PLL microwave synthesizer with fundamental 10 GHz to 20 GHz integrated VCO and output divider covering 625 MHz to 20 GHz with 18 fs RMS jitter.

Operating Conditions:

• Supply voltage: 3.15 V to 3.45 V (3.3 V supplies) and 4.75 V to 5.25 V (5 V supplies)
• Operating temperature: -40°C to +105°C
• Output frequency range: 625 MHz to 20 GHz
• Reference input frequency: 10 MHz to 4500 MHz

Absolute Maximum Ratings:

• Max supply voltage: 3.6 V (3.3 V supplies to GND), 5.5 V (5 V supplies to GND)
• Max junction/storage temperature: 150°C (junction), -55°C to +150°C (storage)

Key Specs:

• Fundamental VCO frequency: 10 GHz to 20 GHz
• Normalized in-band phase noise floor: -239 dBc/Hz (integer mode)
• Phase noise floor: -156 dBc/Hz (at 20 GHz carrier)
• Integrated RMS jitter: 18 fs (at 20 GHz, 100 Hz to 100 MHz bandwidth)
• Maximum PFD input frequency: 625 MHz (integer mode), 250 MHz (fractional mode)
• Differential RF output power: 10 dBm (fOUT = 11 GHz), 5 dBm (fOUT = 20 GHz)
• Charge pump output current: 0.79 mA to 11.1 mA (programmable)
• Reference to output propagation delay: 190 ps typ (delay tempco 0.06 ps/°C)

Features:

• Fundamental octave VCO from 10 GHz to 20 GHz eliminating subharmonic filters
• Output dividers (1, 2, 4, 8, 16) covering 625 MHz to 20 GHz
• VCO autocalibration time <100 μs
• Reference to output delay adjustment step size <1 ps
• Multichip output phase alignment capability
• 3-wire or 4-wire SPI interface up to 75 MHz and dedicated 2-wire phase adjust interface
• On-chip 8-bit ADC temperature sensor

Applications:

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement

Package:

• 48-terminal LGA (7 mm × 7 mm, package type CC-48-10)

• Fundamental VCO frequency range: 10 GHz to 20 GHz
• VCO phase noise improvement of up to 3 dB as compared to ADF4382
• Integrated RMS jitter at 20 GHz = 18 fs (integration bandwidth: 100 Hz to 100 MHz)
• Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
• VCO fast calibration time: <2 μs
• VCO autocalibration time: <100 μs
• Phase noise floor: -156 dBc/Hz at 20 GHz
• PLL specifications
• -239 dBc/Hz: normalized in-band phase noise floor (integer mode)
• -287 dBc/Hz: normalized 1/f phase noise floor
• 625 MHz maximum phase/frequency detector input frequency
• 4.5 GHz reference input frequency
• Typical spurious f PFD : -90 dBc
• Reference to output delay specifications
• Propagation delay temperature coefficient: 0.06 ps/°C
• Adjustment step size: <1 ps
• Multichip output phase alignment
• 3.3 V and 5 V power supplies
• ADIsimPLL ™ loop filter design tool support
• 7 mm × 7 mm, 48-terminal LGA
• -40°C to +105°C operating temperature

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement

Figure 1. ADF4383 Functional Block Diagram

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

TA = 25°C, unless otherwise noted.

Table 3. Absolute Maximum Ratings

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.

θ JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θ JC-TOP and θ JC-BOTTOM are the junction-to-case thermal resistance top and bottom.

Table 4. Thermal Resistance