VS1053B

Part: VS1053b - VLSI Solution

Type: Audio Codec Circuit

Key Specs:

• Clock frequency: 12-13 MHz (single), 24-26 MHz (optional)
• Instruction RAM: 16 KiB
• Data RAM: 0.5+ KiB
• DAC resolution: 18-bit
• Earphone driver load: 30 Ω
• WMA bitrate support: 5-384 kbps

Features:

• Decodes Ogg Vorbis, MP3 (MPEG 1 & 2 audio layer III CBR +VBR +ABR), MP1/MP2 (layers I & II optional), MPEG4 / 2 AAC-LC(+PNS), HE-AAC v2 (Level 3) (SBR + PS), WMA 4.0/4.1/7/8/9 all profiles, FLAC (with software plugin), WAV (PCM + IMA ADPCM), General MIDI 1 / SP-MIDI format 0 files
• Encodes Ogg Vorbis (with software plugin)
• Encodes stereo IMA ADPCM / PCM
• Streaming support for MP3 and WAV
• EarSpeaker Spatial Processing
• Bass and treble controls
• Internal PLL clock multiplier
• Low-power operation
• High-quality on-chip stereo DAC with no phase error between channels
• Zero-cross detection for smooth volume change
• Stereo earphone driver
• Quiet power-on and power-off
• I2S interface for external DAC
• Separate voltages for analog, digital, I/O
• On-chip RAM for user code and data
• Serial control and data interfaces
• Can be used as a slave co-processor
• SPI flash boot for special applications
• UART for debugging purposes
• Up to 8 GPIO pins
• Lead-free RoHS-compliant package (Green)
• High-quality variable-sample-rate stereo ADC (mic, line, line + mic or 2×line)
• Optional factory-programmable unique chip ID

Applications:

• null

Package:

• Lead-free RoHS-compliant package (Green): dimensions not specified

VLSI

Solution y

• Decodes
  • Ogg Vorbis; MP3 = MPEG 1 & 2 audio layer III (CBR +VBR +ABR); MP1/MP2 = layers I & II optional; MPEG4 / 2 AAC-LC(+PNS), HE-AAC v2 (Level 3) (SBR + PS); WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); FLAC with software plugin; WAV (PCM + IMA ADPCM); General MIDI 1 / SP-MIDI format 0 files
• Encodes Ogg Vorbis w/ software plugin
• Encodes stereo IMA ADPCM / PCM
• Streaming support for MP3 and WAV
• EarSpeaker Spatial Processing
• Bass and treble controls
• Operates with a single 12..13 MHz clock
• Can also be used with a 24..26 MHz clock
• Internal PLL clock multiplier
• Low-power operation
• High-quality on-chip stereo DAC with no phase error between channels
• Zero-cross detection for smooth volume change
• Stereo earphone driver capable of driving a 30 Ω load
• Quiet power-on and power-off

5.1 Packages

LPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment.

5.1.1 LQFP-48

Figure 1: Pin Configuration, LQFP-48.

LQFP-48 package dimensions are at http://www.vlsi.fi/ .

Figure 2: VS1053b in LQFP-48 Packaging.

Pad Name	LQFP	Pin	Function
	Pin	Type
MICP / LINE1	1	AI	Positive differential mic input, self-biasing / Line-in 1
MICN	2	AI	Negative differential mic input, self-biasing
XRESET	3	DI	Active low asynchronous reset, schmitt-trigger input
DGND0	4	DGND	Core & I/O ground
CVDD0	5	CPWR	Core power supply
IOVDD0	6	IOPWR	I/O power supply
CVDD1	7	CPWR	Core power supply
DREQ	8	DO	Data request, input bus
GPIO2 / DCLK1	9	DIO	General purpose IO 2 / serial input data bus clock
GPIO3 / SDATA1	10	DIO	General purpose IO 3 / serial data input
GPIO6 / I2S SCLK3	11	DIO	General purpose IO 6 / I2S SCLK
GPIO7 / I2S SDATA3	12	DIO	General purpose IO 7 / I2S SDATA
XDCS / BSYNC1	13	DI	Data chip select / byte sync
IOVDD1	14	IOPWR	I/O power supply
VCO	15	DO	For testing only (Clock VCO output)
DGND1	16	DGND	Core & I/O ground
XTALO	17	AO	Crystal output
XTALI	18	AI	Crystal input
IOVDD2	19	IOPWR	I/O power supply
DGND2	20	DGND	Core & I/O ground
DGND3	21	DGND	Core & I/O ground
DGND4	22	DGND	Core & I/O ground
XCS	23	DI	Chip select input (active low)
CVDD2	24	CPWR	Core power supply
GPIO5 / I2S MCLK3	25	DIO	General purpose IO 5 / I2S MCLK
RX	26	DI	UART receive, connect to IOVDD if not used
TX	27	DO	UART transmit
SCLK	28	DI	Clock for serial bus
SI	29	DI	Serial input
SO	30	DO3	Serial output
CVDD3	31	CPWR	Core power supply
XTEST	32	DI	Reserved for test, connect to IOVDD
GPIO0	33	DIO	Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor2
GPIO1	34	DIO	General purpose IO 1
GND	35	DGND	I/O Ground
GPIO4 / I2S LROUT3	36	DIO	General purpose IO 4 / I2S LROUT
AGND0	37	APWR	Analog ground, low-noise reference
AVDD0	38	APWR	Analog power supply
RIGHT	39	AO	Right channel output
AGND1	40	APWR	Analog ground
AGND2	41	APWR	Analog ground
GBUF	42	AO	Common buffer for headphones, do NOT connect to ground!
AVDD1	43	APWR	Analog power supply
RCAP	44	AIO	Filtering capacitance for reference
AVDD2	45	APWR	Analog power supply
LEFT	46	AO	Left channel output
AGND3	47	APWR	Analog ground
LINE2	48	AI	Line-in 2 (right channel)

¹ First pin function is active in New Mode, latter in Compatibility Mode.

² Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details.

3 If I2S CF ENA is '0' the pins are used for GPIO. See Chapter 10.13 for details.

Pin types:

Type	Description
DI	Digital input, CMOS Input Pad
DO	Digital output, CMOS Input Pad
DIO	Digital input/output
DO3	Digital output, CMOS Tri-stated Output Pad
AI	Analog input

Type	Description
AO	Analog output
AIO	Analog input/output
APWR	Analog power supply pin
DGND	Core or I/O ground pin
CPWR	Core power supply pin
IOPWR	I/O power supply pin

6 Connection Diagram, LQFP-48

Figure 3: Typical Connection Diagram Using LQFP-48.

Figure 3 shows a typical connection diagram for VS1053.

Figure Note 1: Connect either Microphone In or Line In, but not both at the same time.

Note: This connection assumes SM SDINEW is active (see Chapter 8.7.1). If also SM SDISHARE is used, xDCS should be tied low or high (see Chapter 7.2.1).

The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1053b may be connected directly to the earphone connector.

GBUF must NOT be connected to ground under any circumstances. If GBUF is not used, LEFT and RIGHT must be provided with coupling capacitors. To keep GBUF stable, you should always have the resistor and capacitor even when GBUF is not used. See application notes for details.

Unused GPIO pins should have a pull-down resistor. Unused line and microphone inputs should not be connected.

If UART is not used, RX should be connected to IOVDD and TX be unconnected.

Do not connect any external load to XTALO.

¹ Higher current can cause latch-up.

² Must not exceed 3.6 V

Parameter	Symbol	Min	Typ	Max	Unit
Ambient Operating Temperature		-30		+85	◦C
1 Analog and Digital Ground	AGND DGND		0.0		V
Positive Analog, REF=1.23V	AVDD	2.5	2.8	3.6	V
2 Positive Analog, REF=1.65V	AVDD	3.3	3.3	3.6	V
Positive Digital	CVDD	1.7	1.8	1.85	V
I/O Voltage	IOVDD	1.8	2.8	3.6	V
3 Input Clock Frequency	XTALI	12	12.288	13	MHz
Internal Clock Frequency	CLKI	12	36.864	55.3	MHz
4 Internal Clock Multiplier		1.0×	3.0×	4.5×
Master Clock Duty Cycle		40	50	60	%

¹ Must be connected together as close the device as possible for latch-up immunity.

² Reference voltage can be internally selected between 1.23V and 1.65V, see section 8.7.2.

³ The maximum sample rate that can be played with correct speed is XTALI/256 (or XTALI/512 if SM CLK RANGE is set). Thus, XTALI must be at least 12.288 MHz (24.576 MHz) to be able to play 48 kHz at correct speed.

⁴ Reset value is 1.0×. Recommended SC MULT=3.5×, SC ADD=1.0× (SCI CLOCKF=0x8800). Do not exceed maximum specification for CLKI.