VS1053A/B
VS1053b - Ogg Vorbis/MP3/AAC/WMA/FLAC/ MIDI AUDIO CODEC CIRCUIT
Manufacturer
VLSI Solution
Overview
Part: VS1053b
Type: Ogg Vorbis/MP3/AAC/WMA/FLAC/ MIDI AUDIO CODEC CIRCUIT
Key Specs:
- Operates with a single 12..13 MHz clock
- Can also be used with a 24..26 MHz clock
- Stereo earphone driver capable of driving a 30 Ω load
- 16 KiB instruction RAM
- 0.5+ KiB data RAM
- Up to 8 general purpose I/O pins
- WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps)
- 18-bit oversampling, multi-bit, sigma-delta DAC
Features:
- Decodes Ogg Vorbis; MP3 = MPEG 1 & 2 audio layer III (CBR +VBR +ABR); MP1/MP2 = layers I & II optional; MPEG4 / 2 AAC-LC(+PNS), HE-AAC v2 (Level 3) (SBR + PS); WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); General MIDI 1 / SP-MIDI format 0 files; FLAC with software plugin; WAV (PCM + IMA ADPCM)
- Encodes Ogg Vorbis w/ software plugin
- Encodes stereo IMA ADPCM / PCM
- Streaming support for MP3 and WAV
- EarSpeaker Spatial Processing
- Bass and treble controls
- Internal PLL clock multiplier
- Low-power operation
- High-quality on-chip stereo DAC with no phase error between channels
- Zero-cross detection for smooth volume change
- Stereo earphone driver
- Quiet power-on and power-off
- I2S output interface for external DAC
- Separate voltages for analog, digital, I/O
- On-chip RAM for user code and data
- Serial control and data interfaces
- Can be used as a slave co-processor
- SPI flash boot for special applications
- UART for debugging purposes
- New functions may be added with software and up to 8 GPIO pins
- Lead-free RoHS-compliant package
Applications:
- null
Package:
- Lead-free RoHS-compliant package: null
Features
- Decodes Ogg Vorbis; MP3 = MPEG 1 & 2 audio layer III (CBR +VBR +ABR); MP1/MP2 = layers I & II optional; MPEG4 / 2 AAC-LC(+PNS), HE-AAC v2 (Level 3) (SBR + PS); WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); General MIDI 1 / SP-MIDI format 0 files; FLAC with software plugin; WAV (PCM + IMA ADPCM)
- Encodes Ogg Vorbis w/ software plugin
- Encodes stereo IMA ADPCM / PCM
- Streaming support for MP3 and WAV
- EarSpeaker Spatial Processing
- Bass and treble controls
- Operates with a single 12..13 MHz clock
- Can also be used with a 24..26 MHz clock
- Internal PLL clock multiplier
- Low-power operation
- High-quality on-chip stereo DAC with no phase error between channels
- Zero-cross detection for smooth volume change
- Stereo earphone driver capable of driving a 30 Ω load
- Quiet power-on and power-off
- I2S output interface for external DAC
- Separate voltages for analog, digital, I/O
- On-chip RAM for user code and data
- Serial control and data interfaces
- Can be used as a slave co-processor
- SPI flash boot for special applications
- UART for debugging purposes
- New functions may be added with software and up to 8 GPIO pins
- Lead-free RoHS-compliant package
Pin Configuration
7.1.1 VS10xx Native Modes (New Mode, recommended)
These modes are active on VS1053b when SM_SDINEW is set to 1 (default at startup). DCLK and SDATA are not used for data transfer and they can be used as general-purpose I/O pins (GPIO2 and GPIO3). BSYNC function changes to data interface chip select (XDCS).
| SDI Pin | SCI Pin | Description |
|---|---|---|
| XDCS | XCS | Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. If SM_SDISHARE is 1, pin XDCS is not used, but the signal is generated internally by inverting XCS. |
| SCK | Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. | |
| SI | Serial input. If a chip select is active, SI is sampled on the rising CLK edge. | |
| - | SO | Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. |
7.1.2 VS1001 Compatibility Mode (deprecated, do not use in new designs)
This mode is active when SM_SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.
| SDI Pin | SCI Pin | Description |
|---|---|---|
| - | XCS | Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. |
| BSYNC | - | SDI data is synchronized with a rising edge of BSYNC. |
| DCLK | SCK | Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. |
| SDATA | SI | Serial input. SI is sampled on the rising SCK edge, if XCS is low. |
| - | SO | Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. |
Absolute Maximum Ratings
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Analog Positive Supply | AVDD | -0.3 | 3.6 | V |
| Digital Positive Supply | CVDD | -0.3 | 1.85 | V |
| I/O Positive Supply | IOVDD | -0.3 | 3.6 | V |
| Current at Any Non-Power Pin1 | ±50 | mA | ||
| Voltage at Any Digital Input | -0.3 | IOVDD+0.32 | V | |
| Operating Temperature | -40 | +85 | ◦C | |
| Storage Temperature | -65 | +150 | ◦C |
1 Higher current can cause latch-up.
2 Must not exceed 3.6 V
Recommended Operating Conditions
| Parameter | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Ambient Operating Temperature | -40 | +85 | ◦C | ||
| Analog and Digital Ground 1 | AGND DGND | 0.0 | V | ||
| Positive Analog, VREF=1.23V 2 | AVDD12 | 2.6 | 2.8 | 3.6 | V |
| Positive Analog, VREF=1.65V 2 | AVDD16 | 3.3 | 3.3 | 3.6 | V |
| Positive Digital | CVDD | 1.7 | 1.8 | 1.85 | V |
| I/O Voltage | IOVDD | 1.8 | 2.8 | 3.6 | V |
| Input Clock Frequency 3 | XTALI | 12 | 12.288 | 13 | MHz |
| Internal Clock Frequency | CLKI | 12 | 36.864 | 55.3 | MHz |
| Internal Clock Multiplier 4 | CLKM | 1.0× | 3.0× | 4.5× | |
| Master Clock Duty Cycle | 40 | 50 | 60 | % |
1 Must be connected together as close the device as possible for latch-up immunity.
2 Reference voltage can be internally selected between 1.23V and 1.65V, see section 9.6.2. 3 The maximum sample rate that can be played with correct speed is XTALI/256 (or XTALI/512 if SM_CLK_RANGE is set). Thus, XTALI must be at least 12.288 MHz (24.576 MHz) to be able to play 48 kHz at correct speed.
4 Reset value is 1.0×. Recommended SC_MULT=3.5×, SC_ADD=1.0× (SCI_CLOCKF=0x8800). Do not exceed maximum specification for CLKI.
Related Variants
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