TSL2561FN
Light-to-Digital ConverterThe TSL2561FN is a light-to-digital converter from ams AG. View the full TSL2561FN datasheet below including key specifications, electrical characteristics.
Manufacturer
ams AG
Category
Light-to-Digital Converter
Package
Chipscale, TMB-6, Dual Flat No-Lead - 6, ChipLED-6
Key Specifications
| Parameter | Value |
|---|---|
| Dynamic Range | 1,000,000-to-1 (20-bit effective) |
| Power Down Current | 3.2 µA (Typical) |
| I2C Clock Frequency | 0 to 400 kHz |
| Supply Voltage Range | 2.7V to 3.6V |
| Communication Interface | I2C |
| Active Power Consumption | 0.75 mW (Typical) |
| Programmable Analog Gain | Yes |
| Digital Output Resolution | 16-bit |
| Operating Temperature Range | -30°C to 70°C |
| Programmable Integration Times | 13.7 ms, 101 ms, 402 ms |
Overview
Part: TSL2560 / TSL2561 — ams AG
Type: Light-to-Digital Converter
Description: The TSL2560 and TSL2561 are light-to-digital converters that transform light intensity to a digital signal output, providing a near-photopic response over an effective 20-bit dynamic range with 16-bit resolution, and featuring programmable gain and integration time.
Operating Conditions:
- Supply voltage: 2.7–3.6 V
- Operating temperature: -30 to 70 °C
- I2C clock frequency: 0–400 kHz (TSL2561)
- SMBus clock frequency: 10–100 kHz (TSL2560)
Absolute Maximum Ratings:
- Max supply voltage: 3.8 V
- Max digital output current: 20 mA
- Max storage temperature: 85 °C
Key Specs:
- Supply current (Active): 0.24 mA (Typ)
- Supply current (Power down): 3.2 μA (Typ)
- INT, SDA output low voltage (3 mA sink): 0.4 V (Max)
- INT, SDA output low voltage (6 mA sink): 0.6 V (Max)
- Leakage current: -5 to 5 μA
- Conversion time: 12 ms (Min), 100 ms (Typ), 400 ms (Max)
- Data setup time: 100 ns (Min)
- Input pin capacitance: 10 pF (Max)
Features:
- Approximates Human Eye Response
- Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
- 16-Bit Digital Output with SMBus (TSL2560) at 100 kHz or I2C (TSL2561) Fast-Mode at 400 kHz
- Programmable Analog Gain and Integration Time Supporting 1,000,000-to-1 Dynamic Range
- Automatically Rejects 50/60-Hz Lighting Ripple
- Low Active Power (0.75 mW Typical) with Power Down Mode
- RoHS Compliant
Applications:
- Display panels (LCD, OLED, etc.) for extending battery life and optimum viewing
- Controlling keyboard illumination
- Exposure control in digital cameras
- Notebook/tablet PCs, LCD monitors, flat-panel televisions, cell phones
- Street light control, security lighting, sunlight harvesting, machine vision, automotive instrumentation clusters
Package:
- Chipscale (CS)
- TMB-6 (T)
- Dual Flat No-Lead - 6 (FN)
- ChipLED-6 (CL)
Electrical Characteristics
| PARAMETER † | PARAMETER † | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| t (CONV) | Conversion time | 12 | 100 | 400 | ms | |
| f f (SCL) | Clock frequency (I 2 C only) | 0 | 400 | kHz | ||
| f f (SCL) | Clock frequency (SMBus only) | 10 | 100 | kHz | ||
| t (BUF) | Bus free time between start and stop condition | 1.3 | μ s | |||
| t (HDSTA) | Hold time after (repeated) start condition. After this period, the first clock is generated. | 0.6 | μ s | |||
| t (SUSTA) | Repeated start condition setup time | 0.6 | μ s | |||
| t (SUSTO) | Stop condition setup time | 0.6 | μ s | |||
| t (HDDAT) | Data hold time | 0 | 0.9 | μ s | ||
| t (SUDAT) | Data setup time | 100 | ns | |||
| t (LOW) | SCL clock low period | 1.3 | μ s | |||
| t (HIGH) | SCL clock high period | 0.6 | μ s | |||
| t (TIMEOUT) | Detect clock/data low timeout (SMBus only) | 25 | 35 | ms | ||
| t F | Clock/data fall time | 300 | ns | |||
| t R | Clock/data rise time | 300 | ns | |||
| C i | Input pin capacitance | 10 | pF |
† Specified by design and characterization; not production tested. Technical content still valid ams AG
Typical Application
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Figure 21. Suggested FN Package PCB Layout NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Figure 22. Suggested CL Package PCB Layout Technical content still valid
TAOS059Q - NOVEMBER 2009
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