TPS62140RGTT

Part: TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 from Texas Instruments

Type: Synchronous Step-Down DC-DC Converter

Key Specs:

• Input voltage range: 3 V to 17 V
• Output current: Up to 2 A
• Adjustable output voltage: 0.9 V to 6 V
• Quiescent current: 17 μA (typical)
• Switching frequency: typically 2.5 MHz

Features:

• DCS-Control™ topology
• Pin-selectable output voltage (nominal, +5%)
• Programmable soft start and tracking
• Seamless power-save mode transition
• Selectable operating frequency
• Power-good output
• 100% duty-cycle mode
• Short-circuit protection
• Overtemperature protection
• Pin-to-pin compatible with the TPS62130 and TPS62150

Applications:

• Standard 12-V rail supplies
• POL supply from single or multiple Li-ion battery
• Solid-state drives
• Embedded systems
• LDO replacement
• Mobile PCs, tablets, modems, cameras
• Server, microserver
• Data terminal, point of sales (ePOS)

Package:

• VQFN-16: 3 mm × 3 mm

• DCS-Control™ topology
• Input voltage range: 3 V to 17 V
• Up to 2-A output current
• Adjustable output voltage from 0.9 V to 6 V
• Pin-selectable output voltage (nominal, +5%)
• Programmable soft start and tracking
• Seamless power-save mode transition
• Quiescent current of 17 μA (typical)
• Selectable operating frequency
• Power-good output
• 100% duty-cycle mode
• Short-circuit protection
• Overtemperature protection
• Pin-to-pin compatible with the TPS62130 and TPS62150
• Available in a 3-mm × 3-mm, VQFN-16 package
• Use the TPS82140 for faster designs

• Standard 12-V rail supplies
• POL supply from single or multiple Li-ion battery
• Solid-state drives
• Embedded systems
• LDO replacement
• Mobile PCs, tablets, modems, cameras
• Server, microserver
• Data terminal, point of sales (ePOS)

Figure 6-1. 16-Pin VQFN RGT Package (Top View)

Table 6-1. Pin Functions

• (1) For more information about connecting pins, see Section 8 and Section 9.
• (2) Connect FSW to VOUT or PG in this case.
• (3) An internal pulldown resistor keeps the logic level low, if pin is floating.

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating junction temperature range (unless otherwise noted)

7.2 ESD Ratings

⁽¹⁾ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

7.4 Thermal Information

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

⁽²⁾ All voltages are with respect to network ground terminal.

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

⁽³⁾ ESD testing is performed according to the respective JESD22 JEDEC standard.

7.5 Electrical Characteristics

over operating junction temperature (TJ= –40°C to 125°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)

⁽²⁾ Current into AVIN + PVIN pins

⁽³⁾ This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Section 8.4.4).

⁽⁴⁾ This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the fixed-voltage versions the (internal) resistive divider is included.

⁽⁵⁾ Line and load regulation depend on external component selection and layout (see Figure 9-16 and Figure 9-17).

7.6 Typical Characteristics

8 Detailed Description

8.1 Overview

The TPS6214x synchronous switched-mode power converters are based on DCS-Control (Direct Control with Seamless Transition into Power-Save Mode), an advanced regulation topology that combines the advantages of hysteretic, voltage mode, and current mode control including an ac loop directly associated with the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady-state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.

The DCS-Control topology supports Pulse Width Modulation (PWM) mode for medium and heavy load conditions and Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5 MHz or 1.25 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode, the switching frequency decreases linearly with the load current. Because DCS-Control supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage.

Fixed output-voltage versions provide the smallest solution size and lowest current consumption, requiring only three external components. An internal current limit supports nominal output currents of up to 2 A.

The TPS6214x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.

8.2 Functional Block Diagrams

^* This pin is connected to a pull down resistor internally (see Section 8.3)

Figure 8-1. TPS62140 and TPS62140A (Adjustable Output Voltage)

^* This pin is connected to a pull down resistor internally (see Section 8.3)

Figure 8-2. TPS62141/2/3 (Fixed Output Voltage)

8.3 Feature Description

8.3.1 Enable/Shutdown (EN)

When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5 μA. During shutdown, the internal power MOSFETs and entire control circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must be set externally to High or Low. An internal pulldown resistor of about 400 kΩ is connected and keeps EN logic low if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High.

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails.

8.3.2 Soft-Start/Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of about 50 μs, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See Figure 9-34 and Figure 9-35 for typical start-up operation.

Using a very small capacitor (or leaving SS/TR pin un-connected) provides fastest start-up behavior. There is no theoretical limit for the longest start-up time. The TPS6214x can start into a pre-biased output. During monotonic pre-biased start-up, both the power MOSFETs are not allowed to turn on until the internal ramp of the device sets an output voltage above the pre-bias voltage. As long as the output is below about 0.5 V, a reduced current limit of typically 1.6 A is set internally. If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new start-up sequence as set by the SS/TR connection.

A voltage supplied to SS/TR can be used for tracking a primary voltage. The output voltage follows this voltage in both directions, up and down (see Section 9).

8.3.3 Power Good (PG)

The TPS6214x has a built-in power-good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and maintain its specified logic-low level. With the TPS62140, it is high-impedance when the device is turned off due to EN, UVLO, or thermal shutdown. The TPS62140A features PG = Low in this case and can be used to actively discharge VOUT (see Figure 9-41). VIN must remain present for the PG pin to stay Low. See TPS62130A Differences to TPS62130 Application Report for application details. If not used, the PG pin should be connected to GND but may be left floating.

Table 8-1. Power Good Pin Logic Table (TPS62140)

8.3.4 Pin-Selectable Output Voltage (DEF)

The output voltage of the TPS6214x devices can be increased by 5% above the nominal voltage by setting the DEF pin to High¹ . When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed information on voltage margining using the TPS6214x can be found in Voltage Margining Using the TPS62130 Application Report. A pulldown resistor of about 400 kΩ is internally connected to the pin, ensuring a proper logic level if the pin is high impedance or floating after initially set to Low. The resistor is disconnected if the pin is set High.

8.3.5 Frequency Selection (FSW)

To get high power density with very small solution size, a high switching frequency allows the use of small external components for the output filter. However switching losses increase with the switching frequency. If efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz typ.) by pulling FSW to high. It is mandatory to start with FSW = low to limit inrush current, which can be done by connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output current at the lower switching frequency, it is recommended to use an inductor of at least 2.2 μH. The switching frequency can be changed during operation, if needed. A pulldown resistor of about 400 kΩ is internally connected to the pin, acting the same way as at the DEF pin (see above).

¹ Maximum allowed voltage is 7 V. Therefore, it is recommended to connect it to VOUT or PG, not VIN.

8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents incorrect operation of the device by switching off both the power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.

8.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_J exceeds 160°C (typ.), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes high-impedance. When T_J decreases below the hysteresis amount, the converter resumes normal operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal shutdown temperature.

8.4 Device Functional Modes

8.4.1 Pulse-Width Modulation (PWM) Operation

The TPS6214x operates with pulse-width modulation in continuous-conduction mode (CCM) with a nominal switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is controlled and depends on V_IN , V_OUT , and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor ripple current.

8.4.2 Power Save Mode Operation

The TPS6214x enters its built-in power-save mode seamlessly if the load current decreases. This secures a high efficiency in light-load operation. The device remains in power-save mode as long as the inductor current is discontinuous.

In power-save mode, the switching frequency decreases linearly with the load current, maintaining high efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is seamless in both directions.

TPS6214x includes a fixed-on-time circuit. An estimate for this on-time, in steady-state operation with FSW = low, is:

$t_ON = frac{V_OUT}{V_IN} · 400ns tag{1}$

For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can reach its minimum value at high duty cycles. The output voltage remains regulated in such case. Using t_ON, the typical peak inductor current in Power Save Mode can be approximated by:

$I_LPSM(peak) = frac{(V_IN - V_OUT)}{L} · t_ON$ (2)

When $V_{IN}decreases to typically 15% above VOUT, the TPS6214x does not enter power-save mode, regardless of the load current. The device maintains output regulation in PWM mode.


8.4.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D = VOUT/VIN and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty-cycle operation, turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input-to-output voltage differences, for example, for the longest operation time of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, is calculated as:V_IN(min) = V_OUT(min) + I_OUT ≤ft( R_DS(on) + R_L right) tag{3}$

where

• I_OUT is the output current
• R_DS(on) is the R_DS(on) of the high-side FET
• R_L is the DC resistance of the inductor used

8.4.4 Current Limit and Short Circuit Protection

The TPS6214x devices are protected against heavy load and short-circuit events. If a short circuit is detected (VOUT drops below 0.5 V), the current limit is reduced to 1.6 A, typically. If the output voltage rises above 0.5 V, the device runs in normal operation again. At heavy loads, the current limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot through current, then the low-side FET switches on to allow the inductor current to decrease. The low-side current limit is typically 2.4 A. The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side current-limit threshold.

The output current of the device is limited by the current limit (see Section 7.5). Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit is calculated as follows:

$I_peak(typ) = I_LIMF + frac{V_L}{L} · t_PD tag{4}$

where

• I_LIMF is the static current limit, specified in Section 7.5
• · L is the inductor value
• $V_L$ is the voltage across the inductor $(V_{IN} V_{OUT})$
• t_PD is the internal propagation delay

The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high-side switch peak current is calculated as follows:

$I_peak(typ) = I_LIMF + frac{(V_IN - V_OUT)}{L} · 30ns(5)

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPS62140 is a switched mode step-down converter, able to convert a 3-V to 17-V input voltage into a 0.9-V to 6-V output voltage, providing up to 2 A. It needs a minimum amount of external components. Apart from the LC output filter and the input capacitor, only the TPS62140 (TPS62140A) with an adjustable output voltage needs an additional resistive divider to set the output voltage level.

9.2 Typical Application


Figure 9-1. 3.3-V/2-A Step-Down Converter

9.2.1 Design Requirements

The following design guideline provides a component selection to operate the device within the recommended operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution size and lowest output voltage ripple. For highest efficiency set FSW = high and the device operates at the lower switching frequency. For smallest solution size and lowest output voltage ripple set FSW = low and the device operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V, and T = 25°C, using the external components of Table 9-1.

9.2.2 Detailed Design Procedure

The component selection used for measurements is given as follows:

REFERENCE DESCRIPTION MANUFACTURER(1) IC 17-V, 2-A step-down converter, QFN TPS62140RGT, Texas Instruments L1 2.2-μH, 3.1-A, 0.165 in × 0.165 in XFL4020-222MEB, Coilcraft C1 10-μF, 25-V, ceramic, 1210 Standard C3 22-μF, 6.3-V, ceramic, 0805 Standard C5 3300-pF, 25-V, ceramic, 0603 R1 Dependent on Vout R2 Dependent on Vout R3 100-kΩ, chip, 0603, 1/16W, 1% Standard

Table 9-1. List of Components

(1) See Third-Party Products Disclaimer


9.2.2.1 Programming the Output Voltage

While the output voltage of the TPS62140 (TPS62140A) is adjustable, the TPS62141, TPS62142, and TPS62143 are programmed to fixed output voltages. For fixed output versions, the FB pin is pulled down internally and can be left floating. It is recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection of the resistive divider from Equation 6. It is recommended to choose resistor values which allow a current of at least 2\mu$ A, meaning the value of R2 should not exceed 400 k $\Omega$ . Lower resistor values are recommended for highest accuracy and most-robust design. For applications requiring lowest current consumption, the use of fixed output-voltage versions is recommended.

$R₁ = R₂ ≤ft( frac{V_OUT}{0.8V} - 1 right) tag{6}$

In case the FB pin is opened, the device clamps the output voltage at the VOS pin internally to about 7.4 V.

9.2.2.2 External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TPS6214x is optimized to work within a range of external components. The inductance of the LC output filter and capacitance have to be considered in conjunction, creating a double pole, responsible for the corner frequency of the converter (see Section 9.2.2.4). Table 9-2 can be used to simplify the output filter component selection. Checked cells represent combinations that are proven for stability by simulation and lab test. Further combinations should be checked for each individual application. See Optimizing the TPS62130/40/50/60 Output Filter Application Report for details.

The TPS6214x can be run with an inductor as low as 1 $\mu$ H or 2.2 $\mu$ H. FSW should be set low in this case. However, for applications running with the low-frequency setting (FSW = high) or with low input voltages, 3.3 $\muH is recommended.

Note

DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong influence on the final effective capacitance. Therefore, the right capacitor value must be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance.

9.2.2.2.1 Inductor Selection

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-PSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation

⁽¹⁾ The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%.

⁽²⁾ This LC combination is the standard value and recommended for most applications.


current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static load conditions.I_L(max) = I_OUT(max) + frac{Δ I_L(max)}{2} tag{7}$

$Δ I_L(max) = V_OUT · ≤ft( frac{1 - frac{V_OUT}{V_IN(max)}}{L_(min) · f_SW} right) tag{8}$

where

• I_L(max) is the maximum inductor current
• $\Delta I_Lis the peak-to-peak inductor ripple current
• L(min) is the minimum effective inductor value
• f_SW is the actual PWM switching frequency

Calculating the maximum inductor current using the actual operating conditions gives the minimum required inductor saturation current. It is recommended to add a margin of about 20%. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and size as well. The following inductors have been used with the TPS6214x and are recommended for use:

Table 9-3. List of Inductors

The inductor value also determines the load current at which the power-save mode is entered:

$I_load(PSM) = frac{1}{2} Δ I_L tag{9}Using Equation 8, this current level can be adjusted by changing the inductor value.


9.2.2.2.2 Capacitor Selection

9.2.2.2.1 Output Capacitor

The recommended value for the output capacitor is 22\mu$ F. The architecture of the TPS6214X allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output-voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value can have some advantages, like smaller voltage ripple and a tighter DC output accuracy in power-save mode (see Optimizing the TPS62130/40/50/60 Output Filter Application Report).

Note: In power-save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low ripple.

9.2.2.2.2 Input Capacitor

For most applications, $10~\mu F$ is sufficient and is recommended, though a larger value reduces input-current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied from the same input source, it is recommended to place a capacitance of 0.1 uF from AVIN to AGND, to avoid potential noise coupling.

9.2.2.2.3 Soft-Start Capacitor

A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the output voltage. A constant-current source provides 2.5 μA to charge the external capacitance. The capacitor required for a given soft-start ramp time for the output voltage is given by:

$C_SS = t_SS · frac{2.5 μ A}{1.25 V} [F]$ (10)

where

• C_SS is the capacitance (F) required at the SS/TR pin
• t_SS is the desired soft-start ramp time (s).

9.2.2.3 Tracking Function

If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the FB pin tracks the SS/TR pin voltage as described in Equation 11 and shown in Figure 9-2.

$V_FB ≈ 0.64 · V_SS/TR tag{11}

Figure 9-2. Voltage Tracking Relationship

Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V.

If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero, independent of the tracking voltage. Figure 9-3 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function.


Figure 9-3. Sequence for Ratiometric and Simultaneous Startup

The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as VOUT1.

A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric start-up sequence happens if both supplies are sharing the same soft-start capacitor. Equation 10 calculates the soft-start time, though the SS/TR current must be doubled. Details about these and other tracking and


sequencing circuits are found in Sequencing and Tracking With the TPS621-Family and TPS821-Family Application Report.

Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a wider tolerance than specified.

9.2.2.4 Output Filter and Loop Stability

The devices of the TPS6214x family are internally compensated to be stable with L-C filter combinations corresponding to a corner frequency to be calculated with Equation 12:f_LC = frac{1}{2π√{L · C}} tag{12}$

Proven nominal values for inductance and ceramic capacitance are given in Table 9-2 and are recommended for use. Different values may work, but care must be taken on the loop stability, which is affected. More information including a detailed L-C stability matrix can be found in Optimizing the TPS62130/40/50/60 Output Filter Application Report.

The TPS6214x devices, both fixed and adjustable versions, include an internal 25 pF feed-forward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14:

$f_zero = frac{1}{2π · R₁ · 25 pF} tag{13}$

$f_pole = frac{1}{2π · 25 pF} · ≤ft(frac{1}{R₁} + frac{1}{R₂}right) tag{14}Though the TPS6214x devices are stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in power-save mode and/or improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion on the optimization for stability vs transient response can be found in Optimizing Transient Response of Internally Compensated DC-DC Converters Application Report and Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family Application Report.


9.2.3 Application Curves

VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)













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9.3 System Examples

9.3.1 LED Power Supply

The TPS62140 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid excessive power loss. Because this pin provides 2.5\muA, the feedback pin voltage can be adjusted by an external resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62140. Figure 9-40 shows an application circuit, tested with analog dimming:


Figure 9-40. Single Power LED Supply

The resistor at SS/TR sets the FB voltage to a level of about 300 mV and is calculated from Equation 15.V_FB = 0.64 · 2.5 μ A · R_SS/TR tag{15}The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage accordingly. The minimum input voltage must be rated according to the forward voltage needed by the LED used. More information is available in the application note Step-Down LED Driver With Dimming With the TPS621-Family and TPS821-Family Application Report.

9.3.2 Active Output Discharge

The TPS62140A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown. Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 9-41). The discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability, keep the maximum current into the PG pin less than 10mA.


Figure 9-41. Discharge Vout through PG Pin With TPS62140A


9.3.3 Inverting Power Supply

The TPS6214x can be used as inverting power supply by rearranging external circuitry as shown in Figure 9-42. As the former GND node now represents a voltage level below system ground, the voltage difference between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).V_IN + |V_OUT| ≤ V_{IN max} tag{16}

Figure 9-42. –3.3V Inverting Power Supply

The transfer function of the inverting power supply configuration differs from the buck mode transfer function, incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output capacitance of at least 22μF is recommended. A detailed design example is given in Using the TPS6215x in an Inverting Buck-Boost Topology Application Report.

9.3.4 Various Output Voltages

The following example circuits show how to use the various devices and configure the external circuitry to furnish different output voltages at 2A.


Figure 9-43. 5-V/2-A Power Supply


Figure 9-44. 3.3-V/2-A Power Supply


Figure 9-45. 2.5-V/2-A Power Supply


Figure 9-46. 1.8-V/2-A Power Supply



Figure 9-47. 1.5-V/2-A Power Supply


Figure 9-48. 1.2-V/2-A Power Supply


Figure 9-49. 1-V/2-A Power Supply

10 Power Supply Recommendations

The TPS6214X are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's output current needs to be rated according to the output voltage and the output current of the power rail application.

11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS6214x demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.

See Figure 11-1 for the recommended layout of the TPS6214x, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power line/plane as shown in Section 11.2.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (that is, SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane.

The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation.

The recommended layout is implemented on the EVM and shown in its Users Guide, TPS6213x Buck Converter Evaluation Module User's Guide. Additionally, the Gebers for HPA505 EVM are available for download.

11.2 Layout Example



Figure 11-1. Layout Recommendation

11.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
• Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report), and (Semiconductor and IC Package Thermal Metrics Application Report).

The TPS6214X is designed for a maximum operating junction temperature(T_J)$ of 125°C. Therefore, the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed, increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce the thermal resistance. To get improved thermal behavior, it is recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance.

If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation. Experimental data, taken from the TPS62140 EVM, shows the maximum ambient temperature (without additional cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see Figure 9-38).

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Users Guide, SLVU437
• EVM Gerber Data, SLVC394
• Thermal Characteristics Application Note, SZZA017 and SPRA953

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

DCS-Control™ and TI E2E™ are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 9-Nov-2025

PACKAGING INFORMATION

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⁽¹⁾ Status: For more details on status, see our product life cycle.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.

**Important Information and Disclaimer:**The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

⁽²⁾ Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

⁽³⁾ RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

⁽⁴⁾ Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

⁽⁵⁾ MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

⁽⁶⁾ Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

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TAPE AND REEL INFORMATION

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

*All dimensions are nominal

over operating junction temperature (TJ= –40°C to 125°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)

⁽²⁾ Current into AVIN + PVIN pins

⁽³⁾ This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Section 8.4.4).

⁽⁴⁾ This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the fixed-voltage versions the (internal) resistive divider is included.

⁽⁵⁾ Line and load regulation depend on external component selection and layout (see Figure 9-16 and Figure 9-17).

over operating junction temperature range (unless otherwise noted)

over operating junction temperature range (unless otherwise noted)

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

⁽²⁾ All voltages are with respect to network ground terminal.

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

⁽³⁾ ESD testing is performed according to the respective JESD22 JEDEC standard.