TPS61023
TPS61023 3.7-A Boost Converter with 0.5-V Ultra-low Input Voltage
Manufacturer
ti
Overview
Part: TPS61023
Type: Synchronous Boost Converter
Key Specs:
- Input voltage range: 0.5 V to 5.5 V
- Output voltage setting range: 2.2 V to 5.5 V
- Valley switching current limit: 3.7 A
- Efficiency: 94% at V_IN = 3.6 V, V_OUT = 5 V
- Switching frequency: 1-MHz (when V_IN > 1.5 V), 0.5-MHz (when V_IN < 1 V)
- Shutdown current: 0.1-µA
- Reference voltage accuracy: ±2.5% over -40°C to +125°C
- MOSFETs: Two 47-mΩ (LS) / 68-mΩ (HS)
Features:
- 1.8-V Minimum input voltage for start-up
- Auto PFM operation mode at light load
- Pass-through mode when V_IN > V_OUT
- True disconnection between input and output during shutdown
- Output overvoltage protection
- Thermal shutdown protection
- Output short-circuit protection
- 5.7-V output overvoltage protection
- Consumes 20μA quiescent current from V_OUT in light load condition
Applications:
- Electronic shelf label
- Video doorbell
- Remote controller
- Portable equipment
- Smart devices
- Super capacitor backup power applications
Package:
- SOT563 (DRL) 6-pin: 1.2-mm × 1.6-mm
Features
- Input voltage range: 0.5 V to 5.5 V
- 1.8-V Minimum input voltage for start-up
- Output voltage setting range: 2.2 V to 5.5 V
- Two 47-m $\Omega$ (LS) / 68-m $\Omega$ (HS) MOSFETs
- 3.7-A Valley switching current limit
- 94% Efficiency at $V_{IN}$ = 3.6 V, $V_{OUT}$ = 5 V and $I_{OUT}$
- 1-MHz Switching frequency when VIN > 1.5 V and 0.5-MHz switching frequency when $V_{IN} < 1 \text{ V}$
- Typical 0.1-µA shutdown current from VIN and SW
- ±2.5% Reference voltage accuracy over -40°C to +125°C
- · Auto PFM operation mode at light load
- Pass-through mode when $V_{IN} > V_{OUT}$
- True disconnection between input and output during shutdown
- Output overvoltage and thermal shutdown protections
- Output short-circuit protection
- 1.2-mm × 1.6-mm SOT563 (DRL) 6-pin package
Applications
- Electronic shelf label
- Video doorbell
- Remote controller
3 Description
TPS61023 device is a synchronous boost converter with 0.5-V ultra-low input voltage. The device provides a power supply solution for portable equipment and smart devices powered by various batteries and super capacitors. The TPS61023 has typical 3.7-A valley switch current limit over full temperature range. With a wide input voltage range of 0.5 V to 5.5 V, the TPS61023 supports super capacitor backup power applications, which may deeply discharge the super capacitor.
The TPS61023 operates at 1-MHz switching frequency when the input voltage is above 1.5 V. The switching frequency decreases gradually to 0.5 MHz when the input voltage is below 1.5 V down to 1 V. The TPS61023 enters power-save mode at light load condition to maintain high efficiency over the entire load current range. The TPS61023 consumes a 20μA quiescent current from VOUT in light load condition. During shutdown, the TPS61023 is completely disconnected from the input power and only consumes a 0.1-µA current to achieve long battery life. The TPS61023 has 5.7-V output overvoltage protection, output short circuit protection, and thermal shutdown protection.
The TPS61023 offers a very small solution size with 1.2-mm × 1.6-mm SOT563 (DRL) package and minimum amount of external components.
Device Information
| PART NUMBER | PACKAGE (1) | BODY SIZE (NOM) |
|---|---|---|
| TPS61023 | SOT563 (6) | 1.20 mm × 1.60 mm |
For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Circuit
Pin Configuration
Figure 5-1. DRL Package 6-Pin SOT563 Top View
Pin Functions
| PIN | |
|---|---|
| NO. | NAME |
| 1 | FB |
| 2 | EN |
| 3 | VIN |
| 4 | GND |
| 5 | SW |
| 6 | VOUT |
Electrical Characteristics
$T_J = -40$ °C to 125°C, $V_{IN} = 3.6$ V and $V_{OUT} = 5.0$ V. Typical values are at $T_J = 25$ °C (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUP | PLY | |||||
| V IN | Input voltage range | 0.5 | 5.5 | V | ||
| V IN rising | 1.7 | 1.8 | V | |||
| $V_{IN_UVLO}$ | Under-voltage lockout threshold | V IN falling | 0.4 | 0.5 | V | |
| Quiescent current into VIN pin | IC enabled, No load, No switching $V_{IN}$ = 1.8 V to 5.5 V, $V_{FB}$ = $V_{REF}$ + 0.1 V, $T_J$ up to 85°C | 0.9 | 3.0 | μA | ||
| IQ | Quiescent current into VOUT pin | IC enabled, No load, No switching $V_{OUT}$ = 2.2 V to 5.5 V, $V_{FB}$ = $V_{REF}$ + 0.1 V, $T_{J}$ up to 85°C | 20 | 30 | μA | |
| I SD | Shutdown current into VIN and SW pin | IC disabled, V IN = V SW = 3.6 V, T J = 25°C | 0.1 | 0.2 | μA | |
| OUTPUT | ' | |||||
| V OUT | Output voltage setting range | 2.2 | 5.5 | V | ||
| D. ( | PWM mode | 580 | 595 | 610 | mV | |
| $V_{REF}$ | Reference voltage at the FB pin | PFM mode | 585 | 601 | mV | |
| V OVP | Output over-voltage protection threshold | V OUT rising | 5.5 | 5.7 | 6.0 | V |
| V OVP_HYS | Over-voltage protection hysteresis | 0.1 | V | |||
| Lastra as assessed at ED with | T J = 25°C | 4 | 20 | nA | ||
| I FB_LKG | Leakage current at FB pin | T J = 125°C | 6 | nA | ||
| I VOUT_LKG | Leakage current into VOUT pin | IC disabled, V IN = 0 V, V SW = 0 V, V OUT = 5.5 V, T J = 25°C | 1 | 3 | μΑ | |
| t SS | Soft startup time | From active EN to VOUT regulation. $V_{IN} = 2.5 \text{ V}, V_{OUT} = 5.0 \text{ V}, C_{OUT_EFF} = 10 \mu F, I_{OUT} = 0$ | 700 | μs | ||
| POWER SWI | тcн | ' | ||||
| High-side MOSFET on resistance | V OUT = 5.0 V | 68 | mΩ | |||
| R DS(on) | Low-side MOSFET on resistance | V OUT = 5.0 V | 47 | mΩ | ||
| £ | Control in a few annual control | V IN = 3.6 V, V OUT = 5.0 V, PWM mode | 1.0 | MHz | ||
| $f_{SW}$ | Switching frequency | V IN = 1.0 V, V OUT = 5.0 V, PWM mode | 0.5 | MHz | ||
| t ON_min | Minimum on time | 40 | 96 | 130 | ns | |
| t OFF_min | Minimum off time | 80 | 120 | ns | ||
| I LIM_SW | Valley current limit | V IN = 3.6 V, V OUT = 5.0 V | 2.7 | 3.7 | Α | |
| Des als areas accessed | V IN = 1.8 - 5.5 V, V OUT < 0.4 V | 200 | 350 | mA | ||
| I LIM_CHG | Pre-charge current | V IN = 2.4 V, V OUT = 2.15 V | 750 | 1200 | mA | |
| LOGIC INTE | RFACE | ' | ||||
| V EN_H | EN logic high threshold | V IN > 1.8 V or V OUT > 2.2 V | 1.2 | V | ||
| V EN_L | EN logic low threshold | V IN > 1.8 V or V OUT > 2.2 V | 0.35 | 0.42 | 0.45 | V |
| PROTECTIO | N . | · | ||||
| T SD | Thermal shutdown threshold | T J rising | 150 | °C | ||
| T SD_HYS | Thermal shutdown hysteresis | T J falling below T SD | 20 | °C |
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN, EN, FB, SW, VOUT | –0.3 | 7 | V | |
| Voltage range at terminals(2) | SW spike at 10ns | –0.7 8 V –0.7 9 V –40 150 °C | ||
| SW spike at 1ns | ||||
| Operating junction temperature, TJ | ||||
| Storage temperature, Tstg | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | Input voltage range | 0.5 | 5.5 | V | |
| VOUT | Output voltage setting range | 2.2 | 5.5 | V | |
| L | Effective inductance range | 0.37 | 1.0 | 2.9 | µH |
| CIN | Effective input capacitance range | 1.0 | 4.7 | µF | |
| COUT | Effective output capacitance range | 4 | 10 | 1000 | µF |
| TJ | Operating junction temperature | –40 | 125 | °C |
6.4 Thermal Information
| TPS61023 | TPS61023 | ||
|---|---|---|---|
| THERMAL METRIC(1) | DRL (SOT563) - 6 PINS | DRL (SOT563) - 6 PINS | |
| Standard | EVM(2) | ||
| RθJA | Junction-to-ambient thermal resistance | 142.7 | 91.4 |
| RθJC | Junction-to-case thermal resistance | 55.7 | N/A |
| RθJB | Junction-to-board thermal resistance | 31.0 | N/A |
| ΨJT | Junction-to-top characterization parameter | 1.4 | 5.3 |
| ΨJB | Junction-to-board characterization parameter | 30.7 | 38.1 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Product Folder Links: TPS61023
(2) Measured on TPS61023EVM, 4-layer, 2oz copper 50mm×38mm PCB.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
Thermal Information
| TPS61023 | TPS61023 | ||
|---|---|---|---|
| THERMAL METRIC(1) | DRL (SOT563) - 6 PINS | DRL (SOT563) - 6 PINS | |
| Standard | EVM(2) | ||
| RθJA | Junction-to-ambient thermal resistance | 142.7 | 91.4 |
| RθJC | Junction-to-case thermal resistance | 55.7 | N/A |
| RθJB | Junction-to-board thermal resistance | 31.0 | N/A |
| ΨJT | Junction-to-top characterization parameter | 1.4 | 5.3 |
| ΨJB | Junction-to-board characterization parameter | 30.7 | 38.1 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Product Folder Links: TPS61023
(2) Measured on TPS61023EVM, 4-layer, 2oz copper 50mm×38mm PCB.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
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