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TPA2016D2

Stereo Class-D Audio Amplifier

The TPA2016D2 is a stereo class-d audio amplifier from Texas Instruments. View the full TPA2016D2 datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Category

Stereo Class-D Audio Amplifier

Package

DSBGA (16), QFN (20)

Key Specifications

ParameterValue
PSRR80 dB
Shutdown Current0.2 μA (Typ)
Supply Voltage Range2.5 V to 5.5 V
Selectable Gain Range-28 dB to 30 dB in 1-dB Steps
Communication InterfaceI2C
Audio Frequency Response20 Hz to 20000 Hz
Output Power (4 Ω, 5 V)2.8 W/Ch (10% THD+N)
Output Power (8 Ω, 5 V)1.7 W/Ch (10% THD+N)
Package Dimensions (QFN)4.0 mm × 4.0 mm
Output Power (4 Ω, 3.6 V)1.5 W/Ch (10% THD+N)
Output Power (8 Ω, 3.6 V)750 mW/Ch (10% THD+N)
Package Dimensions (DSBGA)2.2 mm × 2.2 mm
Supply Current (Operating)3.5 mA (Typ)
Class D Switching Frequency275 kHz to 325 kHz
Operating Temperature Range-40 °C to 85 °C

Overview

Part: TPA2016D2 — Texas Instruments

Type: Stereo Class-D Audio Amplifier

Description: A stereo, filter-free Class-D audio power amplifier with a 2.5 V to 5.5 V supply range, capable of driving 2.8 W/Ch into 4 Ω at 5 V or 1.7 W/Ch into 8 Ω at 5 V, featuring programmable Dynamic Range Compression (DRC) and Automatic Gain Control (AGC) via I2C.

Operating Conditions:

  • Supply voltage: 2.5 V to 5.5 V
  • Operating temperature: -40 to 85 °C
  • Minimum load resistance: 3.2 Ω

Absolute Maximum Ratings:

  • Max supply voltage: 6 V
  • Max junction temperature: 150 °C
  • Max storage temperature: 150 °C

Key Specs:

  • Supply current (I_DD): 3.7 mA (Typ, VDD = 3.6 V)
  • Shutdown quiescent current (I_SDZ): 0.2 μA (Typ, VDD = 3.6 V)
  • Class D Switching Frequency (f_SW): 300 kHz (Typ)
  • Start-up time (t_START): 5 ms (Typ)
  • Output offset voltage (V_oo): 2 mV (Typ, VDD = 3.6 V)
  • Power supply rejection ratio (PSRR): -80 dB (Typ, VDD = 2.5 V to 4.7 V)
  • Maximum output power (Po max): 2.8 W (Typ, THD+N = 10%, VDD = 5 V, RL = 4 Ω)
  • Efficiency (η): 90% (Typ, THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO = 0.63W)

Features:

  • Filter-Free Class-D Architecture
  • Power Supply Range: 2.5 V to 5.5 V
  • Flexible Operation With or Without I2C
  • Programmable DRC and AGC Parameters
  • Digital I2C Volume Control
  • Selectable Gain from -28 dB to 30 dB in 1-dB Steps
  • Low Supply Current: 3.5 mA
  • Low Shutdown Current: 0.2 μA
  • High PSRR: 80 dB
  • Fast Start-Up Time: 5 ms
  • Short-Circuit and Thermal Protection

Applications:

  • Wireless or Cellular Handsets and PDAs
  • Portable Navigation Devices
  • Portable DVD Players
  • Notebook PCs
  • Portable Radios
  • Portable Games
  • Educational Toys
  • USB Speakers

Package:

  • DSBGA (16) - 2.20 mm × 2.20 mm
  • QFN (20) - 4.00 mm × 4.00 mm

Features

  • 1 · Filter-Free Class-D Architecture
  • 1.7 W/Ch Into 8 Ω at 5 V (10% THD+N)
  • 750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N)
  • 2.8 W/Ch Into 4 Ω at 5 V (10% THD+N)
  • 1.5 W/Ch Into 4 Ω at 3.6 V (10% THD+N)
  • Power Supply Range: 2.5 V to 5.5 V
  • Flexible Operation With or Without I 2 C
  • Programmable DRC and AGC Parameters
  • Digital I 2 C Volume Control
  • Selectable Gain from -28 dB to 30 dB in 1-dB Steps (When Compression is Used)
  • Selectable Attack, Release, and Hold Times
  • 4 Selectable Compression Ratios
  • Low Supply Current: 3.5 mA
  • Low Shutdown Current: 0.2 μ A
  • High PSRR: 80 dB
  • Fast Start-Up Time: 5 ms
  • AGC Enable or Disable Function
  • Limiter Enable or Disable Function
  • Short-Circuit and Thermal Protection
  • Space-Saving Package
  • -2.2 mm × 2.2 mm Nano-Free™ DSBGA (YZH)

Applications

  • Wireless or Cellular Handsets and PDAs
  • Portable Navigation Devices
  • Portable DVD Players
  • Notebook PCs
  • Portable Radios
  • Portable Games
  • Educational Toys
  • USB Speakers

1

Pin Configuration

TPA2016D2 Pinout

Package: DSBGA (16) 2.20 mm × 2.20 mm

Pin NumberPin NameTypeDescription
A1INR−IRight Channel Input (Negative)
A2INR+IRight Channel Input (Positive)
A3INL+ILeft Channel Input (Positive)
A4INL−ILeft Channel Input (Negative)
B1AVDDPAnalog Supply Voltage
B2SCLII²C Serial Clock
B3SDAI/OI²C Serial Data
B4AGNDPAnalog Ground
C1PVDDRPRight Channel Power Supply Decoupling
C2SDZIShutdown Control (Active Low)
C3PGNDPPower Ground
C4PVDDLPLeft Channel Power Supply Decoupling
D1OUTR+ORight Channel Output (Positive)
D2OUTR−ORight Channel Output (Negative)
D3OUTL−OLeft Channel Output (Negative)
D4OUTL+OLeft Channel Output (Positive)

Notes

  • Pin numbering follows the DSBGA grid layout: columns 1–4 (left to right), rows A–D (top to bottom)
  • AVDD and AGND are analog supply pins; PVDDR, PVDDL, and PGND are power supply decoupling/ground pins
  • SCL and SDA are I²C interface pins for device control and configuration
  • SDZ is an active-low shutdown pin
  • All input and output pins are differential pairs for stereo audio processing

Electrical Characteristics

at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 μ H (unless otherwise noted).

PARAMETERPARAMETERTEST CONDITIONSMINTYPMAXUNIT
V DDSupply voltage rangeSDZ = 0.35 V, V DD = 2.5 V2.53.6
0.1
5.5
1
V
I SDZShutdown quiescent currentSDZ = 0.35 V, V DD = 3.6 V
SDZ = 0.35 V, V DD = 5.5 V
SDZ = 1.3 V, V DD = 2.5 V
0.2
0.3
35
1
1
50
μA
I SWSSoftware shutdown quiescent currentSDZ = 1.3 V, V DD = 3.6 V
SDZ = 1.3 V, V DD = 5.5 V
V DD = 2.5 V
50
75
3.5
70
110
4.5
μA
I DDSupply currentV DD = 3.6 V
V DD = 5.5 V
3.7
4.5
4.7
5.5
mA
f SWClass D Switching Frequency275300325kHz
I IHHigh-level input currentV DD = 5.5 V, SDZ = 5.8 V1μA
I ILLow-level input currentV DD = 5.5 V, SDZ = -0.3 V-1μA
t STARTStart-up time2.5 V ≤ V DD ≤ 5.5 V no pop, C IN ≤ 1 μ F5ms
PORPower on reset ON threshold22.3V
PORPower on reset hysteresis0.2V
CMRRInput common mode rejectionR L = 8 Ω , V icm = 0.5 V and V icm = V DD - 0.8 V, differential inputs shorted-70dB
V ooOutput offset voltageV DD = 3.6 V, A V = 6 dB, R L = 8 Ω , inputs AC-grounded-10210mV
Z OUTOutput Impedance in shutdown modeSDZ = 0.35 V2k Ω
Gain accuracyCompression and limiter disabled, Gain = 0 to 30 dB-0.50.5dB
PSRRPower supply rejection ratioV DD = 2.5 V to 4.7 V-80dB

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted). (1)

MINMAXUNIT
V DDSupply voltageAVDD, PVDDR, PVDDL-0.36V
Input voltageSDZ, INR+, INR-, INL+, INL--0.3V DD + 0.3V
SDA, SCL-0.36V
Continuous total power dissipationContinuous total power dissipationContinuous total power dissipationSee Dissipation RatingsSee Dissipation Ratings
T AOperating free-air temperatureOperating free-air temperature-4085°C
T JOperating junction temperatureOperating junction temperature-40150°C
R LOADMinimum load resistanceMinimum load resistance3.2Ω
T stgStorage temperatureStorage temperature-65150°C

Recommended Operating Conditions

MINMAXUNIT
V DDSupply voltageAVDD, PVDDR, PVDDL2.55.5V
V IHHigh-level input voltageSDZ, SDA, SCL1.3V
V ILLow-level input voltageSDZ, SDA, SCL0.6V
T AOperating free-air temperatureOperating free-air temperature-4085°C

Thermal Information

TPA2016D2TPA2016D2
THERMAL METRIC(1)YZH (DSBGA)RTJ (QFN)
16 PINS20 PINS
R θ JAJunction-to-ambient thermal resistance7133.3
R θ JC(top)Junction-to-case (top) thermal resistance0.422.5
R θ JBJunction-to-board thermal resistance14.49.6
ψ JTJunction-to-top characterization parameter1.90.2
ψ JBJunction-to-board characterization parameter13.69.6
R θ JC(bot)Junction-to-case (bottom) thermal resistance-2.4

Typical Application

Copyright © 2016, Texas Instruments Incorporated

Package Information

SOLDER PAD DEFINITIONSCOPPER PADSOLDER MASK (5) OPENINGCOPPER THICKNESSSTENCIL (6)(7) OPENINGSTENCIL THICKNESS
Non solder mask defined (NSMD)275 μ m (+0.0, -25 μ m)375 μ m (+0.0, -25 μ m)1 oz max (32 μ m)275 μ m × 275 μ m Sq. (rounded corners)125 μ m thick
  • (1) Circuit traces from NSMD defined PWB lands should be 75 μ m to 100 μ m wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
  • (2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application.
  • (3) Recommend solder paste is Type 3 or Type 4.
  • (4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
  • (5) Solder mask thickness should be less than 20 μ m on top of the copper circuit pattern
  • (6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control.
  • (7) Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces.

Figure 45. Land Pattern Dimensions

Ordering Information

MPNPackageTemperature RangePacking
TPA2016D2YZHDSBGA (16)-40 to 85 °C-
TPA2016D2RTJQFN (20)-40 to 85 °C-

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
TPA2012D2Texas Instruments
TPA2016D2BGATexas Instruments
TPA2016D2QFNTexas Instruments
TPA2026D2Texas Instruments
TPA20XXD2Texas Instruments
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