TMS320F28379DPTPQ

Part: TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D, TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D from Texas Instruments

Type: Dual-Core Real-Time Microcontroller

Key Specs:

• CPU Cores: Two TMS320C28x 32-bit CPUs
• CPU Speed: 200MHz
• Flash Memory: 512KB or 1MB
• RAM: 172KB or 204KB
• Core Voltage: 1.2V
• I/O Voltage: 3.3V
• ADC Throughput (12-bit mode): Up to 14MSPS system throughput
• Operating Temperature Range: –40°C to 125°C junction (or free-air for Q-grade)

Features:

• Dual-core architecture with IEEE 754 single-precision FPU, TMU, VCU-II
• Two programmable Control Law Accelerators (CLAs) at 200MHz
• ECC-protected flash and RAM
• Dual-zone security and unique identification number
• Multiple clock sources: two

• Dual-core architecture
  • Two TMS320C28x 32-bit CPUs
  • 200MHz
  • IEEE 754 single-precision Floating-Point Unit (FPU)
  • Trigonometric Math Unit (TMU)
  • Viterbi/Complex Math Unit (VCU-II)
• Two programmable Control Law Accelerators (CLAs)
  • 200MHz
  • IEEE 754 single-precision floating-point instructions
  • Executes code independently of main CPU
• On-chip memory
  • 512KB (256KW) or 1MB (512KW) of flash (ECC-protected)
  • 172KB (86KW) or 204KB (102KW) of RAM (ECC-protected or parity-protected)
  • Dual-zone security supporting third-party development
  • Unique identification number
• Clock and system control
  • Two internal zero-pin 10MHz oscillators
  • On-chip crystal oscillator
  • Windowed watchdog timer module
  • Missing clock detection circuitry
• 1.2V core, 3.3V I/O design
• System peripherals
  • Two External Memory Interfaces (EMIFs) with ASRAM and SDRAM support
  • Dual 6-channel Direct Memory Access (DMA) controllers
  • Up to 169 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering
  • Expanded Peripheral Interrupt controller (ePIE)
  • Multiple Low-Power Mode (LPM) support with external wakeup
• Communications peripherals
  • USB 2.0 (MAC + PHY)
  • Support for 12-pin 3.3V-compatible Universal Parallel Port (uPP) interface
  • Two Controller Area Network (CAN) modules (pin-bootable)
  • Three high-speed (up to 50MHz) SPI ports (pinbootable)
  • Two Multichannel Buffered Serial Ports (McBSPs)
• Four Serial Communications Interfaces (SCI/ UART) (pin-bootable)
• Two I2C interfaces (pin-bootable)
• Analog subsystem
  • Up to four Analog-to-Digital Converters (ADCs)
    • 16-bit mode
      • 1.1MSPS each (up to 4.4MSPS system throughput)
      • Differential inputs
      • Up to 12 external channels
    • 12-bit mode
      • 3.5MSPS each (up to 14MSPS system throughput)
      • Single-ended inputs
      • Up to 24 external channels
    • Single Sample-and-Hold (S/H) on each ADC
    • Hardware-integrated post-processing of ADC conversions
      • Saturating offset calibration
      • Error from setpoint calculation
      • High, low, and zero-crossing compare, with interrupt capability
    • Trigger-to-sample delay capture
  • Eight windowed comparators with 12-bit Digitalto-Analog Converter (DAC) references – Three 12-bit buffered DAC outputs
• Enhanced control peripherals
  • 24 Pulse Width Modulator (PWM) channels with enhanced features
  • 16 High-Resolution Pulse Width Modulator (HRPWM) channels
    • High resolution on both A and B channels of 8 PWM modules
    • Dead-band support (on both standard and high resolution)
  • Six Enhanced Capture (eCAP) modules
  • Three Enhanced Quadrature Encoder Pulse (eQEP) modules
  • Eight Sigma-Delta Filter Module (SDFM) input channels, 2 parallel filters per channel
    • Standard SDFM data filtering
    • Comparator filter for fast action for out of range
• Configurable Logic Block (CLB)
  • Augments existing peripheral capability
  • Supports position manager solutions

• • Functional Safety-Compliant
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 system design up to ASIL D; IEC 61508 up to SIL 3; IEC 60730 up to Class C; and UL 1998 up to Class 2
  • Hardware integrity up to ASIL B, SIL 2
• Safety-related certification
  • ISO 26262 certified up to ASIL B and IEC 61508 certified up to SIL 2 by TUV SUD
• Package options:
  • Lead-free, green packaging
  • 337-ball New Fine Pitch Ball Grid Array (nFBGA) [ZWT suffix]
  • 176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) [PTP suffix]
  • 100-pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix]
• Hardware Built-in Self Test (HWBIST)
• Temperature options:
  • T: –40°C to 105°C junction
  • S: –40°C to 125°C junction
  • Q: –40°C to 125°C free-air (AEC Q100 qualification for automotive applications)

• Medium/short range radar
• Traction inverter motor control
• HVAC large commercial motor control
• Automated sorting equipment
• CNC control
• AC charging (pile) station
• DC charging (pile) station
• EV charging station power module
• Energy storage power conversion system (PCS)
• Central inverter
• Solar power optimizer
• String inverter
• Inverter & motor control
• On-board (OBC) & wireless charger
• Linear motor segment controller
• Servo drive control module
• AC-input BLDC motor drive
• DC-input BLDC motor drive
• Industrial AC-DC
• Three phase UPS

5.1 Pin Diagrams

Figure 5-1 to Figure 5-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array. Each figure shows a quadrant of the terminal assignments. Figure 5-5 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 5-6 shows the pin assignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.

Figure 5-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D** SPRS880P – DECEMBER 2013 – REVISED FEBRUARY 2024 **www.ti.com

Figure 5-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]

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Figure 5-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880P – DECEMBER 2013 – REVISED FEBRUARY 2024 www.ti.com

Figure 5-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]

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Figure 5-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)

Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880P – DECEMBER 2013 – REVISED FEBRUARY 2024 www.ti.com

A. Only the GPIO function is shown on GPIO pins. See Section 5.2.1 for the complete, muxed signal name.

Note

The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package.

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Note

PCB footprints and schematic symbols are available for download in a vendor-neutral format, which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the product folder for each device, under the Packaging section. These footprints and symbols can also be searched for athttps://webench.ti.com/cad/.

Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D

5.2 Signal Descriptions

Section 5.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 4-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are not enabled at reset.

5.2.1 Signal Descriptions

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• NAME
• ADCINA0
• DACOUTA
• ADCINA1
• DACOUTB
• ADCINA2
• CMPIN1P
• ADCINA3
• CMPIN1N
• ADCINA4
• CMPIN2P
• ADCINA5
• CMPIN2N
• ADCINB0
• VDAC
• ADCINB1
• DACOUTC
• ADCINB2
• CMPIN3P
• ADCINB3
• CMPIN3N
• ADCINB4
• ADCINB5
• ADCINC2
• CMPIN6P
• ADCINC3
• CMPIN6N
• ADCINC4
• CMPIN5P
• ADCINC5
• CMPIN5N
• ADCIND0
• CMPIN7P
• ADCIND1
  CMPIN7N

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• NAME
• ADCIND2
• CMPIN8P
• ADCIND3
• CMPIN8N
• ADCIND4
• ADCIND5
• GPIO0
• EPWM1A
• SDAA
• GPIO1
• EPWM1B
• MFSRB
• SCLA
• GPIO2
• EPWM2A
• OUTPUTXBAR1
• SDAB
• GPIO3
• EPWM2B
• OUTPUTXBAR2
• MCLKRB
• OUTPUTXBAR2
• SCLB
• GPIO4
• EPWM3A
• OUTPUTXBAR3
• CANTXA
• GPIO5
• EPWM3B
• MFSRA
• OUTPUTXBAR3
• CANRXA
• GPIO6
• EPWM4A
• OUTPUTXBAR4
• EXTSYNCOUT
• EQEP3A
• CANTXB

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Table 5-1. Signal Descriptions (continued)

• NAME
• VREFHIA
• VREFHIB
• VREFHIC
• VREFHID
• VREFLOA
• VREFLOB
• VREFLOC
• VREFLOD
• ADCIN14
• CMPIN4P
• ADCIN15
• CMPIN4N

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• NAME
• GPIO13
• EPWM7B
• CANRXB
• MDRB
• EQEP1I
• SCIRXDC
• UPP-D7
• GPIO14
• EPWM8A
• SCITXDB
• MCLKXB
• OUTPUTXBAR3
• UPP-D6
• GPIO15
• EPWM8B
• SCIRXDB
• MFSXB
• OUTPUTXBAR4
• UPP-D5
• GPIO16
• SPISIMOA
• CANTXB
• OUTPUTXBAR7
• EPWM9A
• SD1_D1
• UPP-D4
• GPIO17
• SPISOMIA
• CANRXB
• OUTPUTXBAR8
• EPWM9B
• SD1_C1
• UPP-D3
• GPIO18
• SPICLKA
• SCITXDB
• CANRXA
• EPWM10A
• SD1_D2
• UPP-D2

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• NAME
• GPIO19
• SPISTEA
• SCIRXDB
• CANTXA
• EPWM10B
• SD1_C2
• UPP-D1
• GPIO20
• EQEP1A
• MDXA
• CANTXB
• EPWM11A
• SD1_D3
• UPP-D0
• GPIO21
• EQEP1B
• MDRA
• CANRXB
• EPWM11B
• SD1_C3
• UPP-CLK
• GPIO22
• EQEP1S
• MCLKXA
• SCITXDB
• EPWM12A
• SPICLKB
• SD1_D4
• GPIO23
• EQEP1I
• MFSXA
• SCIRXDB
• EPWM12B
• SPISTEB
• SD1_C4
• GPIO24
• OUTPUTXBAR1
• EQEP2A
• MDXB
• SPISIMOB
• SD2_D1

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• NAME
• GPIO25
• OUTPUTXBAR2
• EQEP2B
• MDRB
• SPISOMIB
• SD2_C1
• GPIO26
• OUTPUTXBAR3
• EQEP2I
• MCLKXB
• OUTPUTXBAR3
• SPICLKB
• SD2_D2
• GPIO27
• OUTPUTXBAR4
• EQEP2S
• MFSXB
• OUTPUTXBAR4
• SPISTEB
• SD2_C2
• GPIO28
• SCIRXDA
• EM1CS4
• OUTPUTXBAR5
• EQEP3A
• SD2_D3
• GPIO29
• SCITXDA
• EM1SDCKE
• OUTPUTXBAR6
• EQEP3B
• SD2_C3
• GPIO30
• CANRXA
• EM1CLK
• OUTPUTXBAR7
• EQEP3S
• SD2_D4
• GPIO31
• CANTXA
• EM1WE
• OUTPUTXBAR8
• EQEP3I
• SD2_C4

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Table 5-1. Signal Descriptions (continued)

• NAME
• GPIO32
• SDAA
• EM1CS0
• GPIO33
• SCLA
• EM1RNW
• GPIO34
• OUTPUTXBAR1
• EM1CS2
• SDAB
• GPIO35
• SCIRXDA
• EM1CS3
• SCLB
• GPIO36
• SCITXDA
• EM1WAIT
• CANRXA
• GPIO37
• OUTPUTXBAR2
• EM1OE
• CANTXA
• GPIO38
• EM1A0
• SCITXDC
• CANTXB
• GPIO39
• EM1A1
• SCIRXDC
• CANRXB
• GPIO40
• EM1A2
• SDAB
• GPIO41
• EM1A3
• SCLB
• GPIO42
• SDAA
• SCITXDA
• USB0DM

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• NAME
• GPIO43
• SCLA
• SCIRXDA
• USB0DP
• GPIO44
• EM1A4
• GPIO45
• EM1A5
• GPIO46
• EM1A6
• SCIRXDD
• GPIO47
• EM1A7
• SCITXDD
• GPIO48
• OUTPUTXBAR3
• EM1A8
• SCITXDA
• SD1_D1
• GPIO49
• OUTPUTXBAR4
• EM1A9
• SCIRXDA
• SD1_C1
• GPIO50
• EQEP1A
• EM1A10
• SPISIMOC
• SD1_D2
• GPIO51
• EQEP1B
• EM1A11
• SPISOMIC
• SD1_C2
• GPIO52
• EQEP1S
• EM1A12
• SPICLKC
• SD1_D3

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Table 5-1. Signal Descriptions (continued)

• NAME
• GPIO53
• EQEP1I
• EM1D31
• EM2D15
• SPISTEC
• SD1_C3
• GPIO54
• SPISIMOA
• EM1D30
• EM2D14
• EQEP2A
• SCITXDB
• SD1_D4
• GPIO55
• SPISOMIA
• EM1D29
• EM2D13
• EQEP2B
• SCIRXDB
• SD1_C4
• GPIO56
• SPICLKA
• EM1D28
• EM2D12
• EQEP2S
• SCITXDC
• SD2_D1
• GPIO57
• SPISTEA
• EM1D27
• EM2D11
• EQEP2I
• SCIRXDC
• SD2_C1
• GPIO58
• MCLKRA
• EM1D26
• EM2D10
• OUTPUTXBAR1
• SPICLKB
• SD2_D2
• SPISIMOA

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• NAME
• GPIO59
• MFSRA
• EM1D25
• EM2D9
• OUTPUTXBAR2
• SPISTEB
• SD2_C2
• SPISOMIA
• GPIO60
• MCLKRB
• EM1D24
• EM2D8
• OUTPUTXBAR3
• SPISIMOB
• SD2_D3
• SPICLKA
• GPIO61
• MFSRB
• EM1D23
• EM2D7
• OUTPUTXBAR4
• SPISOMIB
• SD2_C3
• SPISTEA
• GPIO62
• SCIRXDC
• EM1D22
• EM2D6
• EQEP3A
• CANRXA
• SD2_D4
• GPIO63
• SCITXDC
• EM1D21
• EM2D5
• EQEP3B
• CANTXA
• SD2_C4
• SPISIMOB

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Table 5-1. Signal Descriptions (continued)

• NAME
• GPIO64
• EM1D20
• EM2D4
• EQEP3S
• SCIRXDA
• SPISOMIB
• GPIO65
• EM1D19
• EM2D3
• EQEP3I
• SCITXDA
• SPICLKB
• GPIO66
• EM1D18
• EM2D2
• SDAB
• SPISTEB
• GPIO67
• EM1D17
• EM2D1
• GPIO68
• EM1D16
• EM2D0
• GPIO69
• EM1D15
• SCLB
• SPISIMOC
• GPIO70
• EM1D14
• CANRXA
• SCITXDB
• SPISOMIC
• GPIO71
• EM1D13
• CANTXA
• SCIRXDB
• SPICLKC
• GPIO72
• EM1D12
• CANTXB
• SCITXDC
• SPISTEC

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• NAME
• GPIO73
• EM1D11
• XCLKOUT
• CANRXB
• SCIRXDC
• GPIO74
• EM1D10
• GPIO75
• EM1D9
• GPIO76
• EM1D8
• SCITXDD
• GPIO77
• EM1D7
• SCIRXDD
• GPIO78
• EM1D6
• EQEP2A
• GPIO79
• EM1D5
• EQEP2B
• GPIO80
• EM1D4
• EQEP2S
• GPIO81
• EM1D3
• EQEP2I
• GPIO82
• EM1D2
• GPIO83
• EM1D1
• GPIO84
• SCITXDA
• MDXB
• MDXA

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Table 5-1. Signal Descriptions (continued)

• NAME
• GPIO85
• EM1D0
• SCIRXDA
• MDRB
• MDRA
• GPIO86
• EM1A13
• EM1CAS
• SCITXDB
• MCLKXB
• MCLKXA
• GPIO87
• EM1A14
• EM1RAS
• SCIRXDB
• MFSXB
• MFSXA
• GPIO88
• EM1A15
• EM1DQM0
• GPIO89
• EM1A16
• EM1DQM1
• SCITXDC
• GPIO90
• EM1A17
• EM1DQM2
• SCIRXDC
• GPIO91
• EM1A18
• EM1DQM3
• SDAA
• GPIO92
• EM1A19
• EM1BA1
• SCLA
• GPIO93
• EM1BA0
• SCITXDD
• GPIO94
• SCIRXDD
• GPIO95

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• NAME
• GPIO96
• EM2DQM1
• EQEP1A
• GPIO97
• EM2DQM0
• EQEP1B
• GPIO98
• EM2A0
• EQEP1S
• GPIO99
• EM2A1
• EQEP1I
• GPIO100
• EM2A2
• EQEP2A
• SPISIMOC
• GPIO101
• EM2A3
• EQEP2B
• SPISOMIC
• GPIO102
• EM2A4
• EQEP2S
• SPICLKC
• GPIO103
• EM2A5
• EQEP2I
• SPISTEC
• GPIO104
• SDAA
• EM2A6
• EQEP3A
• SCITXDD
• GPIO105
• SCLA
• EM2A7
• EQEP3B
• SCIRXDD
• GPIO106
• EM2A8
• EQEP3S
• SCITXDC

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Table 5-1. Signal Descriptions (continued)

• NAME
• GPIO107
• EM2A9
• EQEP3I
• SCIRXDC
• GPIO108
• EM2A10
• GPIO109
• EM2A11
• GPIO110
• EM2WAIT
• GPIO111
• EM2BA0
• GPIO112
• EM2BA1
• GPIO113
• EM2CAS
• GPIO114
• EM2RAS
• GPIO115
• EM2CS0
• GPIO116
• EM2CS2
• GPIO117
• EM2SDCKE
• GPIO118
• EM2CLK
• GPIO119
• EM2RNW
• GPIO120
• EM2WE
• USB0PFLT
• GPIO121
• EM2OE
• USB0EPEN
• GPIO122
• SPISIMOC
• SD1_D1
• GPIO123
• SPISOMIC
• SD1_C1
• GPIO124
• SPICLKC
• SD1_D2

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• NAME
• GPIO165
• EPWM11A
• GPIO166
• EPWM11B
• GPIO167
• EPWM12A
• GPIO168
• EPWM12B
• XRS
• CLOCKS
• X1
• X2
• NO CONNECT
• NC
• JTAG
• TCK
• TDI
• TDO
• TMS

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• NAME
• TRST
• INTERNAL VOLTAGE REGULATOR CONTROL
• VREGENZ
• ANALOG, DIGITAL, AND I/O POWER
• VDD
• VDD3VFL
• VDDA

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• NAME
• VDDIO
• VDDOSC

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880P – DECEMBER 2013 – REVISED FEBRUARY 2024

• NAME
• VSS

Table 5-1. Signal Descriptions (continued)

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• NAME
• VSS
• VSSOSC
• VSSA
• ERRORSTS

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• NAME
• FLT1
• FLT2

(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance

(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).

(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be performed with the provided IBIS models. The termination is not required if this pin is used for input function.

5.3 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 5-2 lists the pull direction and when it is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a particular package. Other pins noted in Table 5-2 with pullups and pulldowns are always on and cannot be disabled.

Table 5-2. Pins With Internal Pullup and Pulldown

(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

5.4 Pin Multiplexing

5.4.1 GPIO Muxed Pins

Table 5-3 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings.

Table 5-3. GPIO Muxed Pins

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Table 5-3. GPIO Muxed Pins (continued)

Table 5-3. GPIO Muxed Pins (continued)

Table 5-3. GPIO Muxed Pins (continued)

(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.

(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).

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5.4.2 Input X-BAR

The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to external interrupts (XINT) (see Figure 5-7). Table 5-4 shows the input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

Figure 5-7. Input X-BAR

Table 5-4. Input X-BAR Destinations

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5.4.3 Output X-BAR and ePWM X-BAR

The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the Output X-BAR and ePWM X-BAR are shown in Figure 5-8. For details on the Output X-BAR and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

Figure 5-8. Output X-BAR and ePWM X-BAR

5.4.4 USB Pin Muxing

Table 5-5 shows assignment of the alternate USB function mapping. These can be configured with the GPBAMSEL register.

Table 5-5. Alternate USB Function

5.4.5 High-Speed SPI Pin Muxing

The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI when not in high-speed mode (HS_MODE = 0).

To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX registers as shown in Table 5-6.

Table 5-6. GPIO Configuration for High-Speed SPI

5.5 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 5-7 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 5-7, any are acceptable. Pins not listed in Table 5-7 must be connected according to Section 5.2.1.

• VREFHIx
• VREFLOx
• ADCINx
• GPIOx
• X1
• X2
• TCK
• TDI
• TDO
• TMS
• TRST
• VREGENZ
• ERRORSTS
• FLT1
• FLT2
• VDD
• VDDA
• VDDIO
• VDD3VFL
• VDDOSC
• VSS
• VSSA
• VSSOSC

Table 5-7. Connections for Unused Pins

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS, unless otherwise noted.

(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and impact other electrical specifications.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see Semiconductor and IC Package Thermal Metrics.

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6.2 ESD Ratings – Commercial

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings – Automotive

6.4 Recommended Operating Conditions

(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.

(2) Operation above T^J = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded Processors for more information.

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6.5 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute maximum possible. The actual device currents in an application will vary with application code and pin configurations. Section 6.5.1 shows the device current consumption at 200-MHz SYSCLK.

6.5.1 Device Current Consumption at 200-MHz SYSCLK

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6.5.1 Device Current Consumption at 200-MHz SYSCLK (continued)

(1) IDDIO current is dependent on the electrical loading on the I/O pins.

(2) CPU2 must go into IDLE mode before CPU1 enters HALT mode.

(3) CPU2 must go into reset/IDLE/STANDBY mode before CPU1 enters HIBERNATE mode.

(4) MAX: Vmax, 125°C

(5) TYP: Vnom, 30°C

(6) The following is executed in a loop on CPU1:

• All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to I2C-B; McBSP-A to McBSP-B; USB

• SDFM1 to SDFM4 active
• ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
• CPU TIMERs active
• DMA does 32-bit burst transfers
• CLA1 does multiply-accumulate tasks
• All ADCs perform continuous conversion
• All DACs ramp voltage up/down at 150 kHz
• CMPSS1 to CMPSS8 active

The following is executed in a loop on CPU2:

• CPU TIMERs active
• CLA1 does multiply-accumulate tasks
• VCU does complex multiply/accumulate with parallel load
• TMU calculates a cosine
• FPU does multiply/accumulate with parallel load

(7) Brownout events during flash programming can corrupt flash data. Programming environments using alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin to avoid supply brownout conditions.

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6.5.2 Current Consumption Graphs

Figure 6-1 and Figure 6-2 are a typical representation of the relationship between frequency and current consumption/power on the device. The operational test from Section 6.5.1 was run across frequency at Vmax and high temperature. Actual results will vary based on the system implementation and conditions.

Figure 6-1. Operational Current Versus Frequency

Figure 6-2. Power Versus Frequency

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Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current between TYP and MAX conditions can be seen in Figure 6-3. The current consumption in HALT mode is primarily leakage current as there is no active switching if the internal oscillator has been powered down.

Figure 6-3 shows the typical leakage current across temperature. The device was placed into HALT mode under nominal voltage conditions.

Figure 6-3. IDD Leakage Current Versus Temperature

6.5.3 Reducing Current Consumption

The F2837xD devices provide some methods to reduce the device current consumption:

• Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during idle periods in the application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be achieved by turning off the clock to any peripheral that is not used in a given application. Table 6-1 indicates the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual to ensure each module is powered down as well.

Table 6-1. Current on VDD Supply by Various Peripherals (at 200 MHz)

(1) At Vmax and 125°C.

(2) All peripherals are disabled upon reset. Use the PCLKCRx register to individually enable peripherals. For peripherals with multiple instances, the current quoted is for a single module.

• (3) This number represents the current drawn by the digital portion of the ADC, CMPSS, and DAC modules.
• (4) The ePWM is at /2 of SYSCLK.

6.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

(2) The MAX input leakage shown on ADCINB0 is at high temperature.

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6.7 Thermal Resistance Characteristics

6.7.1 ZWT Package

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
• (2) lfm = linear feet per minute

6.7.2 PTP Package

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
• (2) lfm = linear feet per minute

6.7.3 PZP Package

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
• (2) lfm = linear feet per minute

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6.8 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is T^J , the junction temperature, not the ambient temperature. Hence, care should be taken to keep T^J within the specified limits. Tcase should be measured to estimate the operating junction temperature T^J . Tcase is normally measured at the center of the package top-side surface. The thermal application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and definitions.

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6.9 System

6.9.1 Power Sequencing

6.9.1.1 Signal Pin Requirements

Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).

6.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements

The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional operation.

6.9.1.3 VDD Requirements

The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata.

There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When the flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal current source can cause VDD to rise to approximately 1.3 V. There will be zero current load to the external system VDD regulator while in this condition. This is not an issue for most regulators; however, if the system voltage regulator requires a minimum load for proper operation, then an external 82Ω resistor can be added to the board to ensure a minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata.

6.9.1.4 Supply Ramp Rate

The supplies should ramp to full rail within 10 ms. Section 6.9.1.4.1 shows the supply ramp rate.

6.9.1.4.1 Supply Ramp Rate

6.9.1.5 Supply Supervision

An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS low when supplies are outside operational specifications.

Note

If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto the XRS pin.

6.9.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.

A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Figure 6-4 shows the recommended reset circuit.

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Figure 6-4. Reset Circuit

6.9.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

The parameter th(boot-mode) must account for a reset initiated from any of these sources.

CAUTION

Some reset sources are internally driven by the device. Some of these sources will drive XRS low. Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by other devices in the system. The boot configuration has a provision for changing the boot pins in OTP; for more details, see the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.9.2.2 Reset Electrical Data and Timing

Section 6.9.2.2.1 shows the reset ( XRS) timing requirements. Section 6.9.2.2.2 shows the reset ( XRS) switching characteristics. Figure 6-5 shows the power-on reset. Figure 6-6 shows the warm reset.

6.9.2.2.1 Reset ( XRS) Timing Requirements

6.9.2.2.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

• A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Section 5.2.1.
• B. After reset from any source (see Section 6.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

Figure 6-5. Power-on Reset

A. After reset from any source (see Section 6.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

Figure 6-6. Warm Reset

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6.9.3 Clock Specifications

6.9.3.1 Clock Sources

Table 6-2 lists four possible clock sources. Figure 6-7 provides an overview of the device's clocking system.

Table 6-2. Possible Reference Clock Sources

(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).

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6.9.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.

6.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times

Section 6.9.3.2.1.1 shows the frequency requirements for the input clocks. The Crystal Equivalent Series Resistance (ESR) Requirements table shows the crystal equivalent series resistance requirements. Section 6.9.3.2.1.2 shows the X1 input level characteristics when using an external clock source. Section 6.9.3.2.1.4 and Section 6.9.3.2.1.5 show the timing requirements for the input clocks. Section 6.9.3.2.1.6 shows the PLL lock times for the Main PLL and the USB PLL.

6.9.3.2.1.1 Input Clock Frequency

6.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)

over recommended operating conditions (unless otherwise noted)

6.9.3.2.1.3 XTAL Oscillator Characteristics

over recommended operating conditions (unless otherwise noted)

6.9.3.2.1.4 X1 Timing Requirements

6.9.3.2.1.5 AUXCLKIN Timing Requirements

6.9.3.2.1.6 PLL Lock Times

(1) The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata. Cycle count includes code execution of the PLL initialization routine, which could vary depending on compiler optimizations and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock(). For the auxiliary PLL, see InitAuxPll() or SysCtl_setAuxClock().

6.9.3.2.2 Internal Clock Frequencies

Section 6.9.3.2.2.1 provides the clock frequencies for the internal clocks.

6.9.3.2.2.1 Internal Clock Frequencies

(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

(2) Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and the minimum period is 5.15 ns.

6.9.3.2.3 Output Clock Frequency and Switching Characteristics

Section 6.9.3.2.3.1 provides the frequency of the output clock. Section 6.9.3.2.3.2 shows the switching characteristics of the output clock, XCLKOUT.

6.9.3.2.3.1 Output Clock Frequency

6.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

over recommended operating conditions (unless otherwise noted)

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)

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6.9.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 6-8 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as XTAL) and AUXCLKIN.

Figure 6-8. Connecting Input Clocks to a 2837xD Device

6.9.3.4 XTAL Oscillator

6.9.3.4.1 Introduction

The crystal oscillator in this device is an embedded electrical oscillator that, when paired with a compatible quartz crystal (or a ceramic resonator), can generate the system clock required by the device.

6.9.3.4.2 Overview

The following sections describe the components of the electrical oscillator and crystal.

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6.9.3.4.2.1 Electrical Oscillator

The electrical oscillator in this device is a Pierce oscillator. It is a positive feedback inverter circuit that requires a tuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed. This tank circuit oscillates at the fundamental frequency of the crystal. On this device, the oscillator is designed to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure 6-9 illustrates the components of the electrical oscillator and the tank circuit.

Figure 6-9. Electrical Oscillator Block Diagram

6.9.3.4.2.1.1 Modes of Operation

The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.

6.9.3.4.2.1.1.1 Crystal Mode of Operation

In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2. There is an internal bias resistor for the feedback loop so an external one should not be used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in the effective negative resistance.

In this mode of operation, the resultant clock on X1 is passed to the rest of the chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics table for the VIH and VIL requirements of the comparator.

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6.9.3.4.2.1.1.2 Single-Ended Mode of Operation

In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz crystal should not be used in this mode.

In this mode of operation, the clock on X1 is passed to the rest of the chip. See the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input requirements of the buffer.

A single-ended clock may also be connected to GPIO133/AUXCLKIN pin.

6.9.3.4.2.1.2 XTAL Output on XCLKOUT

The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers. See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on.

6.9.3.4.2.2 Quartz Crystal

Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped. Components of the crystal are shown in Figure 6-10 and explained below.

Figure 6-10. Crystal Electrical Representation

Cm (Motional capacitance): Denotes the elasticity of the crystal.

Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but can be approximated as such depending on the values of the other crystal components.

Lm (Motional inductance): Denotes the vibrating mass of the crystal.

C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package capacitance.

CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to the crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter.

Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, while some crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal manufacturer for how the CL is specified in order to use the correct values in calculations.

From Figure 6-9, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, the capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2.

It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates, but the actual value will depend on the PCB in question.

Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has to satisfy both the electrical oscillator and the crystal.

The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, the crystal frequency will increase and vice versa. However, the effect of frequency-pulling is usually very minimal and typically results in less than 10-ppm variation from the nominal frequency.

6.9.3.4.3 Functional Operation

6.9.3.4.3.1 ESR – Effective Series Resistance

Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationship between ESR and the crystal components is indicated below.

$ESR = Rm ^ast ≤ft{ 1 + frac{C0}{CL} right}² tag{7}Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if the effective load capacitance is much greater than the shunt capacitance.

6.9.3.4.3.2 Rneg – Negative Resistance

Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the circuit.

The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation; therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillation sustenance will not be an issue.

Figure 6-11 and Figure 6-12 show the variation between negative resistance and the crystal components for this device. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL) greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer to Table 6-3 for minimum and maximum values for design considerations.

6.9.3.4.3.3 Start-up Time

Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the Rneg > 3x ESR to 5x ESR of the crystal.

Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, the longer the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are not a correct match.

Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and the external components.

6.9.3.4.3.4 DL – Drive Level

Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The maximum drive level specified in the crystal manufacturer's data sheet is usually the maximum the crystal can dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical oscillator is not necessarily the maximum power and depends on the crystal and board components.

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For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the power dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use should be evaluated to make sure all other conditions for start-up and sustained oscillation are met.

6.9.3.4.4 How to Choose a Crystal

Using Crystal Oscillator Specifications as a reference:

• 1. Pick a crystal frequency (for example, 20 MHz).
• 1. Check that the ESR of the crystal <=50 Ω per specifications for 20 MHz.
• 1. Check that the load capacitance requirement of the crystal manufacturer is within 6 pF and 12 pF per specifications for 20 MHz.
  • As mentioned, CL1 and CL2 are in series; so, provided CL1 = CL2, effective load capacitance CL = [CL1]/2.
  • Adding board parasitics to this results in CL = [CL1]/2 + Cstray
• 1. Check that the maximum drive level of the crystal >= 1 mW. If this requirement is not met, a dampening resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd.

6.9.3.4.5 Testing

It is recommended that the user have the crystal manufacturer completely characterize the crystal with their board to ensure the crystal always starts up and maintains oscillation.

Below is a brief overview of some measurements that can be performed:

Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with less than 1-pF input capacitance should be used.

Frequency

• 1. Bring out the XTAL on XCLKOUT.
• 1. Measure this frequency as the crystal frequency.

Negative Resistance

• 1. Bring out the XTAL on XCLKOUT.
• 1. Place a potentiometer in series with the crystal between the load capacitors.
• 1. Increase the resistance of the potentiometer until the clock on XCLKOUT stops.
• 1. This resistance plus the crystal's actual ESR is the negative resistance of the electrical oscillator.

Start-Up Time

• 1. Turn off the XTAL.
• 1. Bring out the XTAL on XCLKOUT.
• 1. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty cycle.

6.9.3.4.6 Common Problems and Debug Tips

Crystal Fails to Start Up

• Go through the How to Choose a Crystal section and make sure there are no violations.

Crystal Takes a Long Time to Start Up

• If a dampening resistor Rd is installed, it is too high.
• If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due to high load capacitance.

6.9.3.4.7 Crystal Oscillator Specifications

6.9.3.4.7.1 Crystal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the application with the chosen crystal.

6.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements

For the Crystal Equivalent Series Resistance (ESR) Requirements table:

• 1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
• 1. ESR = Negative Resistance/3

Table 6-3. Crystal Equivalent Series Resistance (ESR) Requirements

Negative Resistance vs. 10MHz Crystal


Figure 6-11. Negative Resistance Variation at 10 MHz


Negative Resistance vs. 20MHz Crystal


Figure 6-12. Negative Resistance Variation at 20 MHz

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6.9.3.5 Internal Oscillators

To reduce production board costs and application development time, all F2837xD devices contain two independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK). Section 6.9.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module meets the clocking requirements of the application.

Section 6.9.3.5.1 provides the electrical characteristics of the two internal oscillators.

Note

This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies above 194 MHz.

6.9.3.5.1 Internal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)


6.9.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when migrating from the previous generation of MCUs.

This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM), which cannot be erased after it is programmed.

Table 6-4 shows the minimum required flash wait states at different frequencies. Section 6.9.4.1 shows the flash parameters.

Table 6-4. Flash Wait States

(1) Minimum required FRDCNTL[RWAIT].

6.9.4.1 Flash Parameters

• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed

In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used. Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does. Erase time includes Erase verify by the CPU and does not involve any data transfer.

(2) Erase time includes Erase verify by the CPU.

(3) Each sector, by itself, can only be erased/programmed 20,000 times. If you choose to use a sector (or multiple sectors) like an EEPROM, you can erase/program only those sectors (still limited to 20,000 cycles) without erasing/programming the entire Flash memory. Therefore, the total number of W/E cycles from a device perspective can exceed 20,000 cycles. However, even this number should not exceed 100,000 cycles.


Note

The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum Programming Word Size" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata.

6.9.5 RAM Specifications

Table 6-5. CPU1 RAM Parameters

(1) "Number of Buses Available" indicates how many masters (CLA, DMA, CPU) have access to this memory.

Table 6-6. CPU2 RAM Parameters

(1) "Number of Buses Available" indicates how many masters (CLA, DMA, CPU) have access to this memory.

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6.9.6 ROM Specifications

Table 6-7. CPU1 ROM Parameters

(1) "Number of Buses Available" indicates how many masters (CLA, DMA, CPU) have access to this memory.

Table 6-8. CPU2 ROM Parameters

(1) "Number of Buses Available" indicates how many masters (CLA, DMA, CPU) have access to this memory.


6.9.7 Emulation/JTAG

The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.

See Figure 6-13 to see how the 14-pin JTAG header connects to the MCU's JTAG port signals. Figure 6-14 shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used and should be grounded.

The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board components to be reset through JTAG debug probe commands (available only through the 20-pin header).

Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise, each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.

For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints for C28x in CCS.

TMS TDI TDO PD RTCK TCK EMU0 TRST TDIS GND KEY GND GND EMU1 GND TCK TDO TDI TMS TRST GND 1 2 3 4 5 6 7 8 9 10 11 12 ^{13 14} 3.3 V 3.3 V 100 W 2.2 kW 4.7 kW 4.7 kW 3.3 V Distance between the header and the target should be less than 6 inches (15.24 cm). MCU

For more information about JTAG emulation, see the XDS Target Connection Guide.

Figure 6-13. Connecting to the 14-Pin JTAG Header

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Figure 6-14. Connecting to the 20-Pin JTAG Header

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6.9.7.1 JTAG Electrical Data and Timing

Section 6.9.7.1.1 lists the JTAG timing requirements. Section 6.9.7.1.2 lists the JTAG switching characteristics. Figure 6-15 shows the JTAG timing.

6.9.7.1.1 JTAG Timing Requirements

6.9.7.1.2 JTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted)



Figure 6-15. JTAG Timing


6.9.8 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.

The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.9.8.1 GPIO - Output Timing

Section 6.9.8.1.1 shows the general-purpose output switching characteristics. Figure 6-16 shows the generalpurpose output timing.

6.9.8.1.1 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

(1) Rise time and fall time vary with load. These values assume a 40-pF load.

GPIO


Figure 6-16. General-Purpose Output Timing

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6.9.8.2 GPIO - Input Timing

Section 6.9.8.2.1 shows the general-purpose input timing requirements. Figure 6-17 shows the sampling mode.

6.9.8.2.1 General-Purpose Input Timing Requirements

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.


• A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
• B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
• C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
• D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 6-17. Sampling Mode


6.9.8.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.

Sampling period = SYSCLK cycle 2 QUALPRD, if QUALPRD 0 ´ ´ ¹ (4)

In Equation 2, Equation 3, and Equation 4, SYSCLK cycle indicates the time period of SYSCLK.

Sampling period = SYSCLK cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0

Figure 6-18 shows the general-purpose input timing.


Figure 6-18. General-Purpose Input Timing


6.9.9 Interrupts

Figure 6-19 provides a high-level view of the interrupt architecture.

As shown in Figure 6-19, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins.

In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group.


Figure 6-19. External and ePIE Interrupt Sources

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6.9.9.1 External Interrupt (XINT) Electrical Data and Timing

Section 6.9.9.1.1 lists the external interrupt timing requirements. Section 6.9.9.1.2 lists the external interrupt switching characteristics. Figure 6-20 shows the external interrupt timing.

6.9.9.1.1 External Interrupt Timing Requirements

(1) For an explanation of the input qualifier parameters, see Section 6.9.8.2.1.

6.9.9.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)

(1) For an explanation of the input qualifier parameters, see Section 6.9.8.2.1.

(2) This assumes that the ISR is in a single-cycle memory.




6.9.10 Low-Power Modes

This device has three clock-gating low-power modes and a special power-gating mode.

Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.9.10.1 Clock-Gating Low-Power Modes

IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 6-9 describes the effect on the system when any of the clock-gating low-power modes are entered.

6.9.10.2 Power-Gating Low-Power Modes

HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup capability, and can be used to save power during long periods of inactivity. Table 6-10 describes the effects on the system when the HIBERNATE mode is entered.

Table 6-10. Effect of Power-Gating Low-Power Mode on the Device

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6.9.10.3 Low-Power Mode Wakeup Timing

Section 6.9.10.3.1 shows the IDLE mode timing requirements, Section 6.9.10.3.2 shows the switching characteristics, and Figure 6-21 shows the timing diagram for IDLE mode.

6.9.10.3.1 IDLE Mode Timing Requirements

6.9.10.3.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up signal) involves additional latency.

(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.


A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

Figure 6-21. IDLE Entry and Exit Timing Diagram

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Section 6.9.10.3.3 shows the STANDBY mode timing requirements, Section 6.9.10.3.4 shows the switching characteristics, and Figure 6-22 shows the timing diagram for STANDBY mode.

6.9.10.3.3 STANDBY Mode Timing Requirements

(1) QUALSTDBY is a 6-bit field in the LPMCR register.

6.9.10.3.4 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

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• A. IDLE instruction is executed to put the device into STANDBY mode.
• B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
• C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
• D. The external wake-up signal is driven active.
• E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
• F. After a latency period, the STANDBY mode is exited.
• G. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-22. STANDBY Entry and Exit Timing Diagram

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Section 6.9.10.3.5 shows the HALT mode timing requirements, Section 6.9.10.3.6 shows the switching characteristics, and Figure 6-23 shows the timing diagram for HALT mode.

6.9.10.3.5 HALT Mode Timing Requirements

(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/layout external to the device. See the Crystal Oscillator Electrical Characteristics section for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see Section 6.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device.

6.9.10.3.6 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

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• A. IDLE instruction is executed to put the device into HALT mode.
• B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
• C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
• D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
• E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
• F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now exited.
• G. Normal operation resumes.
• H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 6-23. HALT Entry and Exit Timing Diagram

Note

CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the IDLE instruction to enter HALT.

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Section 6.9.10.3.7 shows the HIBERNATE mode timing requirements, Section 6.9.10.3.8 shows the switching characteristics, and Figure 6-24 shows the timing diagram for HIBERNATE mode.

6.9.10.3.7 HIBERNATE Mode Timing Requirements

6.9.10.3.8 HIBERNATE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

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• A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE. In dual-core applications, CPU1 should confirm that CPU2 has entered IDLE/STANDBY using the LPMSTAT register.
• B. IDLE instruction is executed to put the device into HIBERNATE mode.
• C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 and CPU2 are powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost.
• D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources.
• E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of the device.
• F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured.
• G. At this point, the device is out of HIBERNATE mode, and the application may continue.
• H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements.
• I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation automatically if it was not taken care of inside of IoRestore. CPU2 will be brought out of reset at this point as well.
• J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information.

Figure 6-24. HIBERNATE Entry and Exit Timing Diagram

Note

• 1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information.
• 1. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE register.

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Note

For applications using both CPU1 and CPU2, TI recommends that the application puts CPU2 in either IDLE or STANDBY before entering HIBERNATE mode. If any GPIOs are used and the state is to be preserved, data can be stored in M0/M1 memory of CPU1 to be reconfigured upon wakeup. This should be done before step A of Figure 6-24.

6.9.11 External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous memories (SRAM, NOR flash) or synchronous memory (SDRAM).

6.9.11.1 Asynchronous Memory Support

The EMIF supports asynchronous memories:

• SRAMs
• NOR Flash memories

There is an external wait input that allows slower asynchronous memories to extend the memory access. The EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually programmable attributes:

• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turnaround time
• Extended wait option with programmable time-out
• Select strobe option

6.9.11.2 Synchronous DRAM Support

The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus. The EMIF has a single SDRAM chip select ( EMIF_CS[0]).

The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the program address bus and can only be accessed through the data bus, which places a restriction on the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the examples in C2000Ware (C2000Ware for C2000 MCUs ) and the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

SDRAM configurations supported are:

• One-bank, two-bank, and four-bank SDRAM devices
• Devices with 8-, 9-, 10-, and 11-column addresses
• CAS latency of two or three clock cycles
• 16-bit/32-bit data bus width
• 3.3-V LVCMOS interface

Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The EMIF module does not support mobile SDRAM devices.

On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to an external SDRAM device will have CAS latency.

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6.9.11.3 EMIF Electrical Data and Timing

6.9.11.3.1 Asynchronous RAM

Section 6.9.11.3.1.1 shows the EMIF asynchronous memory timing requirements. Section 6.9.11.3.1.2 shows the EMIF asynchronous memory switching characteristics. Figure 6-25 through Figure 6-28 show the EMIF asynchronous memory timing diagrams.

6.9.11.3.1.1 EMIF Asynchronous Memory Timing Requirements

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended wait states. Figure 6-26 and Figure 6-28 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics


6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics (continued)

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16– 1], WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information.

(2) E = EMxCLK period in ns.

(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information.

(4) Maximum wait time-out condition.

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11 Asserted Deasserted 2 2 EMxWAIT 14 EMxOE

Figure 6-26. EMxWAIT Read Timing Requirements

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Figure 6-28. EMxWAIT Write Timing Requirements


6.9.11.3.2 Synchronous RAM

Section 6.9.11.3.2.1 shows the EMIF synchronous memory timing requirements. Section 6.9.11.3.2.2 shows the EMIF synchronous memory switching characteristics. Figure 6-29 and Figure 6-30 show the synchronous memory timing diagrams.

6.9.11.3.2.1 EMIF Synchronous Memory Timing Requirements

6.9.11.3.2.2 EMIF Synchronous Memory Switching Characteristics

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Figure 6-29. Basic SDRAM Read Operation

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Figure 6-30. Basic SDRAM Write Operation

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6.10 Analog Peripherals

The analog subsystem module is described in this section.

The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.

The analog subsystem has the following features:

• Flexible voltage references
  • The ADCs are referenced to VREFHIx and VREFLOx pins.
  • VREFHIx pin voltage must be driven in externally.
• The buffered DACs are referenced to VREFHIx and VSSA.
  • Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• The comparator DACs are referenced to VDDA and VSSA.
• Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• Flexible pin usage
  • Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
• Internal connection to VREFLO on all ADCs for offset self-calibration

Figure 6-31 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. Figure 6-32 shows the Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 6-33 shows the Analog Subsystem Block Diagram for the 100-pin PZP package.

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Figure 6-31. Analog Subsystem Block Diagram (337-Ball ZWT)

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Figure 6-32. Analog Subsystem Block Diagram (176-Pin PTP)

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Figure 6-33. Analog Subsystem Block Diagram (100-Pin PZP)

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6.10.1 Analog-to-Digital Converter (ADC)

The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

Each ADC has the following features:

• Selectable resolution of 16 bits or 12 bits
• Ratiometric external reference set by VREFHI and VREFLO
• Differential signal conversions (16-bit mode only)
• Single-ended signal conversions (12-bit mode only)
• Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
  • Software immediate start
  • All ePWMs
  • GPIO XINT2
  • CPU timers
  • ADCINT1 or 2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
  • Saturating offset calibration
  • Error from setpoint calculation
  • High, low, and zero-crossing compare, with interrupt and ePWM trip capability
  • Trigger-to-sample delay capture

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Figure 6-34 shows the ADC module block diagram.


Figure 6-34. ADC Module Block Diagram

6.10.1.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are controlled by each ADC module. Table 6-11 summarizes the basic ADC options and their level of configurability.

(1) Writing these values differently to different ADC modules could cause the ADCs to operate asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously, see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .


6.10.1.1.1 Signal Mode

The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input voltage to the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential signaling mode, the input voltage to the converter is sampled through a pair of input pins, one of which is the positive input (ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is the difference between the two (ADCINxP – ADCINxN). Figure 6-35 shows the differential signaling mode. Figure 6-36 shows the single-ended signaling mode.



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Figure 6-36. Single-ended Signaling Mode

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6.10.1.2 ADC Electrical Data and Timing

Section 6.10.1.2.1 shows the ADC operating conditions for 16-bit differential mode. Section 6.10.1.2.2 shows the ADC characteristics for 16-bit differential mode. Section 6.10.1.2.3 shows the ADC operating conditions for 12-bit single-ended mode. Section 6.10.1.2.4 shows the ADC characteristics for 12-bit single-ended mode. Section 6.10.1.2.5 shows the ADCEXTSOC timing requirements.

6.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

(2) VREFCM = (VREFHI + VREFLO)/2

(3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.

Note

The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.

Note

The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V internally, giving improper ADC conversion or DAC output.

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6.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)(6)

(2) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.

(3) No missing codes.

• (4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
• (5) Maximum DC code deviation due to operation of multiple ADCs simultaneously. (6) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
• VREFHI = 2.5 V and VREFLO = 0 V. (7) One ADC operating while all other ADCs are idle.
• (8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
• (9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
• (10) Value based on characterization.
• (11) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

6.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

Note

The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.

Note

The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V internally, giving improper ADC conversion or DAC output.

6.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)(5)


6.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode) (continued)

over recommended operating conditions (unless otherwise noted)(5)

(2) No missing codes.

• (3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
• (4) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
• (5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
• (6) One ADC operating while all other ADCs are idle.
• (7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
• (8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
• (9) Value based on characterization.
• (10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

6.10.1.2.5 ADCEXTSOC Timing Requirements

(1) For an explanation of the input qualifier parameters, see Section 6.9.8.2.1.


6.10.1.2.6 ADC Input Models

Note

ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.

For differential operation, the ADC input characteristics are given by Section 6.10.1.2.6.1 and Figure 6-37.

6.10.1.2.6.1 Differential Input Model Parameters


Figure 6-37. Differential Input Model