TMS320F28379D-Q1

Part: TMS320F2837xD — Texas Instruments

Type: Dual-Core Real-Time Microcontroller

Description: A powerful 32-bit floating-point microcontroller unit (MCU) with a dual-core C28x architecture, operating at 200MHz, featuring up to 1MB Flash and 204KB RAM, and integrating advanced analog and control peripherals for real-time control applications.

Operating Conditions:

• Supply voltage: 1.2V core, 3.3V I/O
• Operating temperature: -40°C to 125°C (junction or free-air depending on variant)
• CPU frequency: 200MHz

Absolute Maximum Ratings:

• Max junction/storage temperature: 125°C (for S and Q temperature options)

Key Specs:

• CPU Cores: Two TMS320C28x 32-bit CPUs
• CPU Frequency: 200MHz
• Flash Memory: Up to 1MB (512KW) with ECC
• RAM: Up to 204KB (102KW) with ECC or parity
• ADCs: Up to four, 16-bit at 1.1MSPS each (4.4MSPS system throughput) or 12-bit at 3.5MSPS each (14MSPS system throughput)
• PWM Channels: 24 (16 with HRPWM)
• GPIO Pins: Up to 169
• CLA Co-processors: Two, 200MHz, IEEE 754 single-precision floating-point

Features:

• IEEE 754 single-precision Floating-Point Unit (FPU)
• Trigonometric Math Unit (TMU) and Viterbi/Complex Math Unit (VCU-II)
• Dual-zone security and unique identification number
• USB 2.0 (MAC + PHY)
• Two CAN modules, three high-speed SPI ports, four SCI/UART, two I2C interfaces
• Functional Safety-Compliant (ISO 26262 up to ASIL D, IEC 61508 up to SIL 3)
• Configurable Logic Block (CLB)

Applications:

• Industrial motor drives
• Solar inverters and digital power
• Electrical vehicles and transportation
• Sensing and signal processing
• Medium/short range radar
• EV charging stations

Package:

• 337-ball nFBGA (ZWT)
• 176-pin HLQFP (PTP)
• 100-pin HTQFP (PZP)

• Dual-core architecture
• -Two TMS320C28x 32-bit CPUs
• -200MHz
• -IEEE 754 single-precision Floating-Point Unit (FPU)
• -Trigonometric Math Unit (TMU)
• -Viterbi/Complex Math Unit (VCU-II)
• Two programmable Control Law Accelerators (CLAs)
• -200MHz
• -IEEE 754 single-precision floating-point instructions
• -Executes code independently of main CPU
• On-chip memory
• -512KB (256KW) or 1MB (512KW) of flash (ECC-protected)
• -172KB (86KW) or 204KB (102KW) of RAM (ECC-protected or parity-protected)
• -Dual-zone security supporting third-party development
• -Unique identification number
• Clock and system control
• -Two internal zero-pin 10MHz oscillators
• -On-chip crystal oscillator
• -Windowed watchdog timer module
• -Missing clock detection circuitry
• 1.2V core, 3.3V I/O design
• System peripherals
• -Two External Memory Interfaces (EMIFs) with ASRAM and SDRAM support
• -Dual 6-channel Direct Memory Access (DMA) controllers
• -Up to 169 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering
• -Expanded Peripheral Interrupt controller (ePIE)
• -Multiple Low-Power Mode (LPM) support with external wakeup
• Communications peripherals
• -USB 2.0 (MAC + PHY)
• -Support for 12-pin 3.3V-compatible Universal Parallel Port (uPP) interface
• -Two Controller Area Network (CAN) modules (pin-bootable)
• -Three high-speed (up to 50MHz) SPI ports (pinbootable)
• -Two Multichannel Buffered Serial Ports (McBSPs)
• -Four Serial Communications Interfaces (SCI/ UART) (pin-bootable)
• -Two I2C interfaces (pin-bootable)
• Analog subsystem
• -Up to four Analog-to-Digital Converters (ADCs)
• 16-bit mode
• -1.1MSPS each (up to 4.4MSPS system throughput)
• -Differential inputs
• -Up to 12 external channels
• 12-bit mode
• -3.5MSPS each (up to 14MSPS system throughput)
• -Single-ended inputs
• -Up to 24 external channels
• Single Sample-and-Hold (S/H) on each ADC
• Hardware-integrated post-processing of ADC conversions
• -Saturating offset calibration
• -Error from setpoint calculation
• -High, low, and zero-crossing compare, with interrupt capability
• -Trigger-to-sample delay capture
• -Eight windowed comparators with 12-bit Digitalto-Analog Converter (DAC) references
• -Three 12-bit buffered DAC outputs
• Enhanced control peripherals
• -24 Pulse Width Modulator (PWM) channels with enhanced features
• -16 High-Resolution Pulse Width Modulator (HRPWM) channels
• High resolution on both A and B channels of 8 PWM modules
• Dead-band support (on both standard and high resolution)
• -Six Enhanced Capture (eCAP) modules
• -Three Enhanced Quadrature Encoder Pulse (eQEP) modules
• -Eight Sigma-Delta Filter Module (SDFM) input channels, 2 parallel filters per channel
• Standard SDFM data filtering
• Comparator filter for fast action for out of range
• Configurable Logic Block (CLB)
• -Augments existing peripheral capability
• -Supports position manager solutions

• Functional Safety-Compliant
• -Developed for functional safety applications
• -Documentation available to aid ISO 26262 system design up to ASIL D; IEC 61508 up to SIL 3; IEC 60730 up to Class C; and UL 1998 up to Class 2
• -Hardware integrity up to ASIL B, SIL 2
• Safety-related certification
• -ISO 26262 certified up to ASIL B and IEC 61508 certified up to SIL 2 by TUV SUD
• Package options:
• -Lead-free, green packaging
• -337-ball New Fine Pitch Ball Grid Array (nFBGA) [ZWT suffix]
• -176-pin PowerPAD ™ Thermally Enhanced LowProfile Quad Flatpack (HLQFP) [PTP suffix]
• -100-pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix]
• Hardware Built-in Self Test (HWBIST)
• Temperature options:
• -T: -40°C to 105°C junction
• -S: -40°C to 125°C junction
• -Q: -40°C to 125°C free-air (AEC Q100 qualification for automotive applications)

• Medium/short range radar
• Traction inverter motor control
• HVAC large commercial motor control
• Automated sorting equipment
• CNC control
• AC charging (pile) station
• DC charging (pile) station
• EV charging station power module
• Energy storage power conversion system (PCS)
• Central inverter
• Solar power optimizer
• String inverter
• Inverter & motor control
• On-board (OBC) & wireless charger
• Linear motor segment controller
• Servo drive control module
• AC-input BLDC motor drive
• DC-input BLDC motor drive
• Industrial AC-DC
• Three phase UPS

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The TMS320F2837xD supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection.

Performance analog and control peripherals are also integrated on the F2837xD MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals.

Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xD. The uPP interface is a new feature of the C2000 ™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.

Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page.

The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.

Ready to get started? Check out the TMDSCNCD28379D or LAUNCHXL-F28379D evaluation board sand download C2000Ware.

To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Figure 5-1 to Figure 5-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array. Each figure shows a quadrant of the terminal assignments. Figure 5-5 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 5-6 shows the pin assignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.

SPRS880P - DECEMBER 2013 - REVISED FEBRUARY 2024

• A. Only the GPIO function is shown on GPIO terminals. See Section 5.2.1 for the complete, muxed signal name.

Figure 5-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) - [Quadrant B]

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• A. Only the GPIO function is shown on GPIO terminals. See Section 5.2.1 for the complete, muxed signal name.

Figure 5-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) - [Quadrant C]

Figure 5-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) - [Quadrant D]

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• A. Only the GPIO function is shown on GPIO pins. See Section 5.2.1 for the complete, muxed signal name.

Figure 5-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)

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• A. Only the GPIO function is shown on GPIO pins. See Section 5.2.1 for the complete, muxed signal name.

Figure 5-6. 100-Pin PZP PowerPAD HTQFP (Top View)

The exposed lead frame die pad of the PowerPAD ™ package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package.

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PCB footprints and schematic symbols are available for download in a vendor-neutral format, which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the product folder for each device, under the Packaging section. These footprints and symbols can also be searched for at https://webench.ti.com/cad/.

over recommended operating conditions (unless otherwise noted)

over operating free-air temperature range (unless otherwise noted)

Based on the end application design and operational profile, the I DD and I DDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep T J within the specified limits. T case should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and definitions.

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The Typical Applications section details some applications of this device. For a more extensive list of applications, see the Applications section of this data sheet.

• (1) For more information, see Mechanical, Packaging, and Orderable Information.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.